LM4549BVHX/NOPB National Semiconductor, LM4549BVHX/NOPB Datasheet - Page 26

• Manufacturer Part Number: LM4549BVHX/NOPB
• Description: IC AUDIO CODEC 2MULTICH 48-LQFP
• Manufacturer: National Semiconductor
• Type: Audio Codec '97r

Specifications of LM4549BVHX/NOPB

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 89
• Voltage - Supply, Analog: 4.2 V ~ 5.5 V
• Voltage - Supply, Digital: 3.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM4549BVHX

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Multiple Codecs
configured as ’Primary’ either by leaving ID1#, ID0# open
(NC) or by strapping them externally to DV
ply).
The difference between Primary and Secondary codec
modes is in their timing source and in the Tag Bit handling in
Output Frames for Command/Status register access. For a
timing source, a Primary codec divides down by 2 the fre-
quency of the signal on XTAL_IN and also generates this as
the BIT_CLK output for the use of the controller and any
Secondary codecs. Secondary codecs use BIT_CLK as an
input and as their timing source and do not use XTAL_IN or
XTAL_OUT. The use of Tag Bits is described below.
SECONDARY CODEC REGISTER ACCESS
For Secondary Codec access, the controller must set the tag
bits for Command Address and Data in the Output Frame as
invalid (i.e. equal to 0). The Command Address and Data tag
bits are in slot 0, bits 14 and 13 and Output Frames are
those in the SDATA_OUT signal from controller to codec.
The controller must also place the non-zero value (01, 10, or
11) corresponding to the Identity (ID1, ID0) of the target
Secondary Codec into the Codec ID field (slot 0, bits 1 and 0)
in that same Output Frame. The value set in the Codec ID
field determines which of the three possible Secondary Co-
decs is accessed. Unlike a Primary Codec, a Secondary
Codec will disregard the Command Address and Data tag
bits when there is a match between the 2-bit Codec ID value
(slot 0, bits 1 and 0) and the Codec Identity (ID1, ID0).
Instead it uses the Codec-ID/Identity match to indicate that
the Command Address in slot 1 and (if a “write”) the Com-
mand Data in slot 2 are valid.
SLOT 0: TAG bits in Output Frames (controller to codec)
Extended Audio ID register (28h): Support for Multiple Codecs
Frame
Bit 15
Reg
28h
Valid
Extended
Slot 1
Audio ID
Valid
14
Name
Slot 2
Valid
13
D15 D14 D13 D12 D11 D10
ID1
Slot 3
Valid
12
ID0
(Continued)
Slot 4
Valid
11
X
X
10
X
DD
X
(Digital Sup-
9
X
X
D9
8
X
X
26
D8
X
7
X
When reading from a Secondary Codec, the controller must
send the correct Codec ID bits (i.e. the target Codec Identity
in slot 0, bits 1 and 0) along with the read-request bit (slot 1,
bit 19) and target register address (slot 1, bits 18 – 12). To
write to a Secondary Codec, a controller must send the
correct Codec ID bits when slot 1 contains a valid target
register address and “write” indicator bit and slot 2 contains
valid target register data. A write operation is only valid if the
register address and data are both valid and sent within the
same frame. When accessing the Primary Codec, the Codec
ID bits are cleared and the tag bits 14 and 13 resume their
role indicating the validity of Command Address and Data in
slots 1 and 2.
The use of the tag bits in Input Frames (carried by the
SDATA_IN signal) is the same for Primary and Secondary
Codecs.
The Codec Identity is determined by the inverting input pins
ID1#, ID0# (pins 46 and 45) and can be read as the value of
the ID1, ID0 bits (D15, D14) in the Extended Audio ID
register, 28h of the target codec.
Slots in the AC Link Output Frame are always mapped to
carry data to the left DAC channel in slot 3 and data to the
right DAC channel in slot 4. Similarly, slots in AC Link Input
Frames are always mapped such that PCM data from the left
ADC channel is carried by slot 3 and PCM data from the right
ADC channel by slot 4. Output Frames are those carried by
the SDATA_OUT signal from the controller to the codec
while Input Frames are those carried by the SDATA_IN
signal from the codec to the controller.
D7
X
6
X
D6
X
D5
5
X
X
D4
X
4
X
D3
X
3
X
D2
X
2
X
D1
X
VRA X001h
D0
ID1
1
Default
ID0
0