MAX9853ETM+ Maxim Integrated Products, MAX9853ETM+ Datasheet - Page 14

• Manufacturer Part Number: MAX9853ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9853ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 48 KHz
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Snr: 75 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
(AV
10kΩ, R
PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, T
noted. Typical values are at T
Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
14
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
MCLK Duty Cycle
Maximum MCLK Jitter
DIGITAL INPUTS (BCLKS_, LRCLKS_, SDINS_, MCLK, SDA, SCL, FAULTIN)
Input-Voltage High
Input-Voltage Low
Input Hysteresis
Input Leakage Current
FAULTIN Input Low Leakage
Current (MAX9853)
FAULTIN Input High Leakage
Current (MAX9853)
Input Capacitance
CMOS DIGITAL OUTPUTS (BCLKS_, LRCLKS_, SDOUTS_)
Output Low Voltage
Output High Voltage
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (Digital Audio Interface S1 and S2)
BCLK Cycle Time
BCLK High Time
BCLK Low Time
BCLK_ or LRCLK_ Rise and Fall
Time
SDIN_ or LRCLK_ to BCLK_
Rising Set-Up Time
SDIN_ or LRCLK_ to BCLK_
Rising Hold Time
SDOUTS1 Delay Time
SDOUTS2 Delay Time
DD
______________________________________________________________________________________
= CPV
OUTR+
PARAMETER
DD
to R
= +3V, DV
OUTR-
= 10kΩ, C1 = 0.22µF, C2 = C
DD
A
= DV
= +25°C.) (See Functional Diagrams/Typical Operating Circuits).
DDS2
SYMBOL
t
t
t
t
f
I
BCLKM
BCLKH
BCLKS
BCLKL
MCLK
IH
V
t
t
V
t
t
V
t
V
DLY
DLY
I
I
r,
HD
SU
= +1.8V, PV
OH
IH
OL
, I
IL
IH
IL
t
f
IL
Maximum allowable RMS for performance
limits
FAULTIN has internal pullup resistor
I
I
Slave operation
Master operation
Slave operation
Slave operation
Master operation, C
BCI = 0 (see I
BCI = 0 (see I
BCI = 0 (see I
C
BCI = 0 (see I
C
OL
OH
L
L
= 30pF
= 30pF
DD
= 3mA
= 3mA
NREG
= +3.3V, R
= C
2
2
2
2
C register definition)
C register definition)
C register definition),
C register definition),
CONDITIONS
PREG
HP
L
= 32Ω, Z
= 15pF
= C
INTMICBIAS
SPK
= 8Ω + 10µH, R
, C
MBIAS
DV
A
DV
0.7 x
= C
MIN
0.4
45
75
30
30
30
= T
-3
DD
5
DD
REC
REF
MIN
-
= 32Ω, R
= 1µF, MCLK = 13MHz, all
13 / 26
to T
TYP
100
200
308
50
10
7
MAX
OUTL+
, unless otherwise
DV
MAX
0.3 x
0.4
55
+3
30
35
50
3
DD
to R
UNITS
ps
OUTL-
MHz
mV
µA
µA
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
RMS
V
V
V
V
=