MAX9853ETM+ Maxim Integrated Products, MAX9853ETM+ Datasheet - Page 59

• Manufacturer Part Number: MAX9853ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9853ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 48 KHz
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Snr: 75 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 = Enabled.
0 = Disabled.
ENA = 1 enables the headphone sense biases and
powers on the threshold comparator circuitry.
Headphone amplifiers must be disabled and micro-
phone amplifiers and bias resistors must be enabled
for proper headset detection. ENA = 0 powers down
the circuitry and sets HSDET (register 0x01, bits
B5–B0) to 0x00.
1 = Enabled.
0 = Disabled.
SLEEP = 1 places the detection circuitry in low-power
mode and disables normal detect mode. This feature is
most useful when operating the MAX9851/MAX9853 in
1 = MAX9851/MAX9853 operational.
0 = Complete shutdown.
SDALL is an active-low shutdown bit that overrides all
settings and places the entire MAX9851/MAX9853 in
low-power shutdown.
1 = Enable.
0 = Disable.
HFEN = 1 enables the MCLK input and allows all clock
dependent circuitry to operate.
1 = Enable.
0 = Disable.
Table 39. System Bit Descriptions
Stereo Audio CODECs with Microphone, DirectDrive
Analog Low-Frequency Oscillator Enable (LFEN)
0x1A
REG
Headphones, Speaker Amplifiers, or Line Outputs
Headset Detect Low-Power Mode (SLEEP)
SHDN
______________________________________________________________________________________
B7
Headset Detect Enable (ENA)
Clock Input Enable (HFEN)
HFEN
B6
Shutdown
LFEN
B5
(S S H H D D N N )
CPEN
B4
low-power shutdown mode. EXTMICBIASL is monitored
and a hardware interrupt is triggered when a load is
detected. Exit sleep mode to clear the hardware interrupt.
Sleep mode is automatically entered when AV
removed and the battery voltage (PV
See the Headset Detect section.
00 = Headphone sense bias disconnected.
01 = Headphone sense test 1 (standard headphone
detection).
10 = Headphone sense test 2 (balanced mono head-
phone detection).
11 = Reserved.
Set HRMODE = 000 prior to headset detection to dis-
able the headphone amplifiers.
LFEN = 1 enables the analog internal low-frequency
oscillator that is used by the charge pump when MCLK
is disabled.
1 = Enable.
0 = Disable.
Always program to 1 for proper operation.
1 = Charge-pump oscillator derived from MCLK.
0 = Charge-pump oscillator derived from internal oscillator.
CPCLK = 1 configures the charge pump to use MCLK
as a clock source. CPCLK = 0 configures the internal
oscillator to be used instead of the MCLK. CPCLK
must bet set to 1 when the Class D amplifier is
being used (MAX9851 only).
B3
0
Charge-Pump Oscillator Select (CPCLK)
Headset Detect Configuration (HSTEST)
System Control Register (0x1A)
B2
1
Charge-Pump Enable (CPEN)
B1
0
DD
) is still present.
CPCLK
B0
DD
59
is