MAX9853ETM+ Maxim Integrated Products, MAX9853ETM+ Datasheet - Page 45

• Manufacturer Part Number: MAX9853ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9853ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 48 KHz
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Snr: 75 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bits in status registers 0x00 and 0x01 are set when an
alert condition exists. The status bits are only updated if
the corresponding interrupt enable is set in register
0x02. All bits in status register 0x00 are automatically
cleared upon a read operation of the register and will
be set again if the condition remains or occurs following
the read of this register.
1 = DAC or ADC clipping has occurred.
0 = No clipping has occurred.
CLD reports that the DAC input data or ADC output
data is clipping due to an excessive signal amplitude in
the digital signal path at any one of seven locations:
DAC mono mixer (left or right), DAC modulator (left or
right), ADC path highpass filter (left or right), or the
VIBE path modulator. To resolve a clip condition in the
signal path, the DAC gain settings and analog input
gain settings should be lowered. As the CLD bit does
not indicate where the overload has occurred, identify
the source by lowering gains individually.
1 = Volume slewing complete.
0 = No volume slewing sequences have completed
since the status register was last read.
SLD reports that any one of the programmable-gain
arrays or volume controllers has completed slews from
a previous setting to a new programmed setting. If mul-
tiple gain arrays or volume controllers are changed at
the same time, in either the analog or digital domain,
SLD flag will be set after the last slew adjusting in each
domain. SLD also reports when the serial interface soft-
start or soft-stop process has completed.
Table 9. Status Register 0
Stereo Audio CODECs with Microphone, DirectDrive
REG
0x00
Headphones, Speaker Amplifiers, or Line Outputs
CLD
B7
______________________________________________________________________________________
Slew Level Detect Flag (SLD)
SLD
B6
Clip Detect Flag (CLD)
ULK
B5
B4
0
1 = Either the S1 or S2 internal DAC PLL is not locked.
0 = Both the S1 and S2 internal PLLs are locked if
enabled and operating properly.
ULK reports that the digital audio phase-locked loop for
either DAC became unlocked and input digital signal
data is unreliable.
1 = Headset configuration has changed.
0 = No change in headset configuration.
HSD reports changes in HSDET (register 0x01, bits
B5–B0). Regardless of the state of IHSD, any removal or
insertion of a jack (detected by monitoring EXTMICBIASL)
triggers an interrupt on the IRQ line. See the Headset
Detect section. Changes on HSDET are digitally
debounced with an approximate 20ms filter before set-
ting HSD. Valid changes on HSDET are delayed by this
amount. MCLK needs to be applied for a short period of
time (> 1ms) after power-on to initialize this flag.
1 = Current overload has occurred on the speaker
amplifiers.
0 = Current consumption is normal.
For the MAX9851, FAULT indicates that the Class D
output amplifiers have entered a current overload state.
1 = The FAULTIN pin has been pulled low.
0 = FAULTIN pin high.
For the MAX9853, FAULT indicates that the FAULTIN
pin has been pulled low.
B3
0
Headset Configuration Change Flag (HSD)
MAX9853: External Fault Flag (FAULT)
MAX9851: Speaker Fault Flag (FAULT)
Status Registers (0x00, 0x01)
B2
0
Digital PLL Unlock Flag (ULK)
HSD
B1
FAULT
B0
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