ENC28J60-I/SP Microchip Technology, ENC28J60-I/SP Datasheet - Page 69
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ENC28J60-I/SP
Manufacturer Part Number
ENC28J60-I/SP
Description
IC ETHERNET CTRLR W/SPI 28DIP
Manufacturer
Microchip Technology
Specifications of ENC28J60-I/SP
Package / Case
28-DIP (0.300", 7.62mm)
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Operating Supply Voltage
3.1 V to 3.6 V
Supply Current (max)
180 mA
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Ethernet Connection Type
10Base-T
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SP
Manufacturer:
MICROCHIP
Quantity:
6 500
REGISTER 12-4:
REGISTER 12-5:
© 2006 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5
bit 4
bit 3-2
bit 1
bit 0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R-0
R-0
R-x
R-x
r
r
r
r
Reserved: Write as ‘0’, ignore on read
Reserved: Maintain as ‘0’
PLNKIE: PHY Link Change Interrupt Enable bit
1 = PHY link change interrupt is enabled
0 = PHY link change interrupt is disabled
Reserved: Write as ‘0’, ignore on read
PGEIE: PHY Global Interrupt Enable bit
1 = PHY interrupts are enabled
0 = PHY interrupts are disabled
Reserved: Maintain as ‘0’
Reserved: Do not modify
Reserved: Read as ‘0’
PLNKIF: PHY Link Change Interrupt Flag bit
1 = PHY link status has changed since PHIR was last read; resets to ‘0’ when read
0 = PHY link status has not changed since PHIR was last read
Reserved: Read as ‘0’
PGIF: PHY Global Interrupt Flag bit
1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read
0 = No PHY interrupts have occurred
Reserved: Do not modify
Reserved: Read as ‘0’
R-0
R-0
R-x
R-x
r
r
r
r
PHIE: PHY INTERRUPT ENABLE REGISTER
PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER
W = Writable bit
‘1’ = Bit is set
SC = Self-clearing bit
‘1’ = Bit is set
R/W-0
R-0
R-0
R-x
r
r
r
r
PLNKIE
PLNKIF
R/SC-0
R/W-0
R-0
R-x
Preliminary
r
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
R-0
R-x
R-0
r
r
r
r
R/SC-0
PGIF
R-0
R-0
R-x
r
r
r
x = Bit is unknown
x = Bit is unknown
ENC28J60
PGEIE
R/W-0
R-0
R-x
R-x
r
r
r
DS39662B-page 67
R/W-0
R-0
R-x
R-0
r
r
r
r
bit 8
bit 0
bit 8
bit 0