ENC28J60-I/SP Microchip Technology, ENC28J60-I/SP Datasheet - Page 92
![IC ETHERNET CTRLR W/SPI 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
ENC28J60-I/SP
Manufacturer Part Number
ENC28J60-I/SP
Description
IC ETHERNET CTRLR W/SPI 28DIP
Manufacturer
Microchip Technology
Specifications of ENC28J60-I/SP
Package / Case
28-DIP (0.300", 7.62mm)
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Operating Supply Voltage
3.1 V to 3.6 V
Supply Current (max)
180 mA
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Ethernet Connection Type
10Base-T
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SP
Manufacturer:
MICROCHIP
Quantity:
6 500
ENC28J60
Packet Format..................................................................... 31
Pattern Match Filter............................................................. 51
Per Packet Control Byte Format ......................................... 39
PHID Registers ................................................................... 22
PHSTAT Registers.............................................................. 22
PHY Register Summary ...................................................... 20
PHY Registers..................................................................... 19
Pinout Diagrams.................................................................... 1
Pinout I/O Descriptions ......................................................... 4
Power-Down........................................................................ 73
Power-on Reset (POR) ....................................................... 60
R
Read Control Register (RCR) ............................................. 27
Reader Response ............................................................... 92
Reading and Writing to the Buffer ....................................... 17
Receive Buffer..................................................................... 17
Receive Filters .................................................................... 47
Receive Only Reset ............................................................ 60
Receiving Packets............................................................... 43
Registers
DS39662B-page 90
CRC Field ................................................................... 32
Data Field.................................................................... 32
Destination Address .................................................... 32
Padding Field .............................................................. 32
Preamble/Start-of-Frame Delimiter ............................. 31
Source Address .......................................................... 32
Type/Length Field ....................................................... 32
Reading....................................................................... 19
Scanning ..................................................................... 19
Writing ......................................................................... 19
Associated Registers .................................................. 73
Broadcast .................................................................... 52
Hash Table.................................................................. 52
Magic Packet .............................................................. 52
Magic Packet Format .................................................. 52
Multicast ...................................................................... 52
Pattern Match.............................................................. 51
Pattern Match Filter Format ........................................ 51
Unicast ........................................................................ 51
Using AND Logic......................................................... 50
Using OR Logic ........................................................... 49
Associated Registers .................................................. 46
Calculating Buffer Free Space .................................... 45
Calculating Free Receive Buffer Space ...................... 45
Calculating Random Access Address ......................... 44
Freeing Buffer Space .................................................. 45
Reading....................................................................... 44
Status Vectors............................................................. 44
EBSTCON (Ethernet Self-Test Control)...................... 75
ECOCON (Clock Output Control) ................................. 6
ECON1 (Ethernet Control 1) ....................................... 15
ECON2 (Ethernet Control 2) ....................................... 16
EFLOCON (Ethernet Flow Control) ............................ 56
EIE (Ethernet Interrupt Enable)................................... 65
EIR (Ethernet Interrupt Request, Flag) ....................... 66
ERXFCON (Ethernet Receive Filter Control) .............. 48
ESTAT (Ethernet Status) ............................................ 64
MABBIPG (MAC Back-to-Back
MACON1 (MAC Control 1).......................................... 34
MACON3 (MAC Control 3).......................................... 35
MACON4 (MAC Control 4).......................................... 36
MICMD (MII Command) .............................................. 21
MISTAT (MII Status) ................................................... 21
PHCON1 (PHY Control 1)........................................... 61
Inter-Packet Gap)................................................ 36
Preliminary
Reset .................................................................................. 59
S
Serial Peripheral Interface. See SPI.
SPI
System Reset ..................................................................... 60
T
Termination Requirement ..................................................... 7
Timing Diagrams
Transmit Buffer ................................................................... 17
Transmit Only Reset ........................................................... 60
Transmitting Packets .......................................................... 39
Typical ENC28J60-Based Interface...................................... 4
U
Unicast Filter....................................................................... 51
W
WWW, On-Line Support ....................................................... 2
PHCON2 (PHY Control 2) .......................................... 37
PHID (PHY Device ID)................................................ 22
PHIE (PHY Interrupt Enable) ...................................... 67
PHIR (PHY Interrupt Request, Flag)........................... 67
PHLCON (PHY Module LED Control)........................... 9
PHSTAT1 (Physical Layer Status 1)........................... 23
PHSTAT2 (Physical Layer Status 2)........................... 24
MAC and PHY Subsystem Resets ............................. 61
Power-on Reset .......................................................... 60
Receive Only Reset .................................................... 60
System Reset ............................................................. 60
Transmit Only Reset ................................................... 60
Bit Field Clear Command............................................ 29
Bit Field Set Command............................................... 29
Instruction Set............................................................. 26
Overview..................................................................... 25
Read Buffer Memory Command ................................. 28
Read Control Register Command............................... 27
System Reset Command............................................ 30
Write Buffer Memory Command ................................. 29
Write Control Register Command............................... 28
CLKOUT Transition ...................................................... 6
Read Control Register Command (ETH) .................... 27
Read Control Register Command (MAC/MII) ............. 27
SPI Input ..................................................................... 82
SPI Input Timing ......................................................... 25
SPI Output .................................................................. 82
SPI Output Timing ...................................................... 25
System Reset Command Sequence........................... 30
Write Buffer Memory Command Sequence ................ 29
Write Control Register Command Sequence.............. 28
Associated Registers .................................................. 42
Status Vectors ............................................................ 41
© 2006 Microchip Technology Inc.