CS8900A-CQ3Z Cirrus Logic Inc, CS8900A-CQ3Z Datasheet - Page 136

• Manufacturer Part Number: CS8900A-CQ3Z
• Description: IC LAN ETHERNET CTLR 3V 100LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Single Chipr

Specifications of CS8900A-CQ3Z

• Package / Case: 100-LQFP
• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: ISA-BUS
• Voltage - Supply: 3V, 5V
• Current - Supply: 95mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 10BASE- 2 or 10BASE- 5 or 10BASE- F or 10BASE- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1163 - KIT EVAL FOR CS8900A
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1127

10.2 Definitions
Cyclic Redundancy Check
Frame Check Sequence
Frame
Individual Address
Inter-Packet Gap
Jabber
Packet
Receive Collision
Signal Quality Error
Slot Time
Transmit Collision
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The method used to compute the 32-bit frame check sequence (FCS).
The 32-bit field at the end of a frame that contains the result of the cyclic redundancy
check (CRC).
An Ethernet string of data bits that includes the Destination Address (DA), Source
Address (SA), optional length field, Logical Link Control data (LLC data), pad bits (if
needed) and Frame Check Sequence (FCS).
The specific Ethernet address assigned to a device attached to the Ethernet media.
Time interval between packets on the Ethernet. Minimum interval is 9.6 µs.
A condition that results when a Ethernet node transmits longer than between 20 ms
and 150 ms.
An Ethernet string of data bits that includes the Preamble, Start-of-Frame Delimiter
(SFD), Destination Address (DA), Source Address (SA), optional length field, Logical
Link Control data (LLC data), pad bits (if needed) and Frame Check Sequence (FCS).
A packet is a frame plus the Preamble and SFD.
A receive collision occurs when the CI+/CI- inputs are active while a packet is being
received. Applies only to the AUI.
When transmitting on the AUI, the MAC expects to see a collision signal on the
CI+/CI- pair within 64 bit times after the end of a transmission. If no collision occurs,
there is said to be an "SQE error". Applies only to the AUI.
Time required for an Ethernet Frame to cross a maximum length Ethernet network.
One Slot Time equals 512 bit times.
A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or
CI+/CI- (AUI) are active while a packet is being transmitted.
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