LAN9210-ABZJ SMSC, LAN9210-ABZJ Datasheet - Page 131

IC ETHERNET CTLR SGL CHIP 56-QFN

LAN9210-ABZJ

Manufacturer Part Number
LAN9210-ABZJ
Description
IC ETHERNET CTLR SGL CHIP 56-QFN
Manufacturer
SMSC
Datasheet

Specifications of LAN9210-ABZJ

Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
638-1048-6

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9210-ABZJ
Manufacturer:
Standard
Quantity:
2 500
Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
6.4
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
In this mode the upper address inputs are not decoded, and any read of the LAN9210 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9210. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits.
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
RX Data FIFO Direct PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time (see Note below)
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order. Parameters t
t
cycle
minimum.
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.5 RX Data FIFO Direct PIO Read Timing
DATASHEET
131
csh
and t
csl
must be extended using wait states to meet the
MIN
165
32
13
0
0
0
0
TYP
133
MAX
Revision 2.7 (03-15-10)
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns

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