LAN9210-ABZJ SMSC, LAN9210-ABZJ Datasheet - Page 96
![IC ETHERNET CTLR SGL CHIP 56-QFN](/photos/6/82/68204/lan9210-abzj_sml.jpg)
LAN9210-ABZJ
Manufacturer Part Number
LAN9210-ABZJ
Description
IC ETHERNET CTLR SGL CHIP 56-QFN
Manufacturer
SMSC
Datasheet
1.LAN9210-ABZJ.pdf
(147 pages)
Specifications of LAN9210-ABZJ
Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
638-1048-6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9210-ABZJ
Manufacturer:
Standard
Quantity:
2 500
- Current page: 96 of 147
- Download datasheet (2Mb)
Revision 2.7 (03-15-10)
5.3.16
5.3.17
31-16
BITS
BITS
15-0
31:0
Reserved
General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
Word Swap. If this field is set to 00000000h, or anything except
0xFFFFFFFFh, the LAN9210 maps words with address bit A[1]=1 to the
high order words of the CSRs and Data FIFOs, and words with address bit
A[1]=0 to the low order words of the CSRs and Data FIFOs. If this field is
set to 0xFFFFFFFFh, the LAN9210 maps words with address bit A[1]=1 to
the low order words of the CSRs and Data FIFOs, and words with address
bit A[1]=0 to the high order words of the CSRs and Data FIFOs.
Note:
GPT_CNT-General Purpose Timer Current Count Register
This register reflects the current value of the GP Timer.
WORD_SWAP—Word Swap Control
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN9210. The LAN9210 always sends data from the Transmit Data FIFO to the network so
that the low order word is sent first, and always receives data from the network to the Receive Data
FIFO so that the low order word is received first.
Offset:
Offset:
Word swap is used in conjunction with the mixed endian
functionality to determine the final byte ordering. Refer to
3.7.3, "Mixed Endian Support"
DESCRIPTION
DESCRIPTION
90h
98h
DATASHEET
for more information.
96
Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Size:
Size:
Section
32 bits
32 bits
NASR
TYPE
TYPE
R/W
RO
RO
00000000h
DEFAULT
DEFAULT
SMSC LAN9210
FFFFh
Datasheet
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