LAN9210-ABZJ SMSC, LAN9210-ABZJ Datasheet - Page 63

• Manufacturer Part Number: LAN9210-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC

Specifications of LAN9210-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1048-6

Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
3.13.2
RX Packet Format
The RX status words can be read from the RX status FIFO port, while the RX data packets can be
read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can
read them as shown in
status word from the RX status FIFO, to ascertain the data size and any error conditions.
Figure 3.21
appended to the data payload is treated just as an additional 4-bytes within the RX Data FIFO. The
RX checksum is enabled by setting the RXCOE_EN bit in the
Control
Checksum Offload Engine
Register. For more information on the RX checksum, refer to
shows the RX packet format when the RX checksum is enabled. The RX checksum data
Host Read
Order
Last
2nd
1st
Figure
(RXCOE)".
Figure 3.20 RX Packet Format
3.20. It is assumed that the host has previously read the associated
31
ofs + First Data DWORD
Optional offset DWORDn
Optional offset DWORD0
DATASHEET
Optional Pad DWORD0
Optional Pad DWORDn
Last Data DWORD
63
.
.
.
.
.
.
.
.
0
COE_CR—Checksum Offload Engine
Section 3.6.1, "Receive
Revision 2.7 (03-15-10)