LAN9118-MT SMSC, LAN9118-MT Datasheet - Page 71

• Manufacturer Part Number: LAN9118-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9118-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1013

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
5.3.3
30-26
BITS
31
25
24
23
22
21
20
19
18
17
16
15
14
13
Software Interrupt (SW_INT). This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
Reserved
TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit
in TX_CFG is set, and the transmitter is halted.
RX Stopped (RXSTOP_INT).
halted.
RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway
point (7FFFFFFFh to 80000000h).
Reserved
TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount
of data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
GP Timer (GPT_INT). This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
PHY (PHY_INT).
Power Management Event Interrupt (PME_INT). This interrupt is issued
when a Power Management Event is detected as configured in the
PMT_CTRL register. This interrupt functions independent of the PME
signal, and will still function if the PME signal is disabled. Writing a '1'
clears this bit regardless of the state of the PME hardware signal.
Notes:
TX Status FIFO Overflow (TXSO).
FIFO overflows.
Receive Watchdog Time-out (RWT).
packet larger than 2048 bytes has been received.
Receiver Error (RXE).
error. Please refer to
description of the conditions that will cause an RXE.
Transmitter Error (TXE).
transmitter has encountered an error. Please refer to
"Transmitter Errors," on page
will cause a TXE.
INT_STS—Interrupt Status Register
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding
bits acknowledges and clears the interrupt.
Detection of a Power Management Event, and assertion of the PME
signal will not wakeup the LAN9118. The LAN9118 will only wake up
when it detects a host write cycle of any data to the BYTE_TEST
register.
The Interrupt Deassertion interval does not apply to the PME interrupt.
Offset:
Indicates a PHY Interrupt event.
Section 3.13.5, "Receiver Errors," on page 56
Indicates that the receiver has encountered an
DESCRIPTION
When generated, indicates that the
T
52, for a description of the conditions that
his interrupt is issued when the receiver is
58h
DATASHEET
Generated when the TX Status
Interrupt is generated when a
71
Size:
Section 3.12.7,
for a
32 bits
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
RO
RO
RO
Revision 1.5 (07-11-08)
DEFAULT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-