LAN9118-MT SMSC, LAN9118-MT Datasheet - Page 76

IC ETHERNET CTRLR 10/100 100TQFP

LAN9118-MT

Manufacturer Part Number
LAN9118-MT
Description
IC ETHERNET CTRLR 10/100 100TQFP
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet

Specifications of LAN9118-MT

Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
100BASE-TX or 10BASE-T
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1013

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9118-MT
Manufacturer:
SMSC
Quantity:
6
Part Number:
LAN9118-MT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LAN9118-MT
Manufacturer:
SMSC
Quantity:
8 000
Part Number:
LAN9118-MT
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
LAN9118-MT
Quantity:
106
Part Number:
LAN9118-MT-E2
Manufacturer:
INTEL
Quantity:
18
Part Number:
LAN9118-MT-E2
Manufacturer:
SMSC
Quantity:
20 000
Revision 1.5 (07-11-08)
5.3.8
31-16
BITS
13-3
15
14
2
1
0
DESCRIPTION
Reserved.
Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX
status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX
status pointers are cleared to zero.
Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX
data FIFO of all pending data. When a ‘1’ is written, the TX data pointers
are cleared to zero.
Reserved
TX Status Allow Overrun (TXSAO). When this bit is cleared, data
transmission is suspended if the TX Status FIFO becomes full. Setting this
bit high allows the transmitter to continue operation with a full TX Status
FIFO.
Note:
Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is
enabled. Any data in the TX FIFO will be sent. This bit is cleared
automatically when STOP_TX is set and the transmitter is halted.
Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will
finish the current frame, and will then stop transmitting. When the transmitter
has stopped this bit will clear. All writes to this bit are ignored while this bit
is high.
TX_CFG—Transmit Configuration Register
This register controls the transmit functions on the LAN9118 Ethernet Controller.
Offset:
This bit does not affect the operation of the TX Status FIFO Full
interrupt.
70h
DATASHEET
76
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
32 bits
TYPE
R/W
R/W
RO
RO
SC
SC
SC
SMSC LAN9118
DEFAULT
Datasheet
0
0
0
0
0
-
-

Related parts for LAN9118-MT