DS21Q43AT Maxim Integrated Products, DS21Q43AT Datasheet - Page 14

• Manufacturer Part Number: DS21Q43AT
• Description: IC FRAMER E1 QUAD 5V IND 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q43AT

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 32mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Dc: 0319
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NOTES:
1. The Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all
2. Any register address between 60h and 7Fh or between E0h and FFh will allow the status of the
3. Register addresses 09h through 0Fh are reserved for future use.
2.0 PARALLEL PORT
The DS21Q43A is controlled via either a non-multiplexed (MUX=0) or multiplexed (MUX=1) bus by an
external microcontroller or microprocessor. The DS21Q43A can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
the AC Electrical Characteristics for more details.
3.0 CONTROL AND TEST REGISTERS
The operation of the DS21Q43A is configured via a set of seven registers. Typically, the control registers
are only accessed when the system is powered up. Once the DS21Q43A has been initialized, the control
registers will only need to be accessed when there is a change in the system configuration. There are two
Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and
three Common Control Registers (CCR1, CCR2 and CCR3). Each of the seven registers is described in
this section.
The Test Registers at addresses 15, 18, and 19 hex are used by the factory in testing the DS21Q43A. On
power-up, the Test Registers should be set to 00 hex in order for the DS21Q43A to operate properly.
0s) on power-up initialization to insure proper operation.
interrupts to appear on the bus.
5A
5B
5C
5D
5E
4F
50
51
52
53
54
55
56
57
58
59
5F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Transmit Signaling 16.
Transmit Si Bits Align Frame.
Transmit Si Bits Non-Align Frame.
Transmit Remote Alarm Bits.
Transmit Sa4 Bits.
Transmit Sa5 Bits.
Transmit Sa6 Bits.
Transmit Sa7 Bits.
Transmit Sa8 Bits.
Receive Si Bits Align Frame.
Receive Si Bits Non-Align Frame.
Receive Remote Alarm Bits.
Receive Sa4 Bits.
Receive Sa5 Bits.
Receive Sa6 Bits.
Receive Sa7 Bits.
Receive Sa8 Bits.
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DS21Q43A