DS21Q43AT Maxim Integrated Products, DS21Q43AT Datasheet - Page 38

• Manufacturer Part Number: DS21Q43AT
• Description: IC FRAMER E1 QUAD 5V IND 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q43AT

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 32mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Dc: 0319
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data
before the old data will be retransmitted. Via the CCR3.6 bit, the user has the option to use the Transmit
Channel Blocking Registers (TCBRs) to determine on a channel by channel basis, which signaling bits
are to be inserted via the TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from
the TSER pin (the corresponding bit in the TCBRs=0). See the Transmit Data Flow diagram in Section 11
for more details.
8.0 TRANSMIT IDLE REGISTERS
There is a set of five registers in the DS21Q43A that can be used to custom tailor the data that is to be
transmitted onto the E1 line, on a channel by channel basis. Each of the 32 E1 channels can be forced to
have a user defined idle code inserted into them.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
NOTE:
If CCR3.5=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies
that channel data is to be sourced from the RSER pin.
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a timeslot in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first. Via
the CCR3.5 bit, the user has the option to use the TIRs to determine on a channel by channel basis, if data
from the RSER pin should be substituted for data from the TSER pin. In this mode, if the corresponding
bit in the TIRs is set to 1, then data will be sourced from the RSER pin. If the corresponding bit in the
TIRs is set to 0, then data for that channel will sourced from the TSER pin. See the Transmit Data Flow
diagram in Section 11 for more details.
(MSB)
(MSB)
CH16
CH24
CH32
TIDR7
CH8
SYMBOL
SYMBOL
TIDR7
TIDR0
CH32
CH1
CH15
CH23
CH31
CH7
TIDR6
POSITION
POSITION
TIDR.7
TIDR.0
TIR4.7
TIR1.0
CH14
CH22
CH30
CH6
TIDR5
NAME AND DESCRIPTION
Transmit Idle Registers.
0=do not insert the Idle Code into this channel
1=insert the Idle Code into this channel
NAME AND DESCRIPTION
MSB of the Idle Code.
LSB of the Idle Code.
CH13
CH21
CH29
CH5
TIDR4
38 of 60
CH12
CH20
CH28
CH4
TIDR3
CH11
CH19
CH27
CH3
TIDR2
CH10
CH18
CH26
CH2
TIDR1
CH17
CH25
(LSB)
CH1
CH9
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
TIDR0
DS21Q43A
(LSB)