ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 106

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 104. HcATLPTDDoneThresholdCount register: bit allocation
Table 106. HcATLPTDDoneThresholdTimeOut register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
14.9.8 HcATLPTDDoneThresholdCount register (R/W: 51h/D1h)
14.9.9 HcATLPTDDoneThresholdTimeOut register (R/W: 52h/D2h)
R/W
15
15
7
7
0
-
-
-
-
-
-
This register specifies the number of ATL PTDs to be done to trigger an ATL interrupt. If
set to 08h, the Host Controller will trigger the ATL interrupt (in the Hc PInterrupt register)
once every eight ATL PTDs are done.
Remark: Do not write 0000h to this register.
Code (Hex): 51 — read
Code (Hex): D1 — write
Table 105. HcATLPTDDoneThresholdCount register: bit description
This is a time-out register used to generate an ATL interrupt. The value in this register
indicates the maximum allowable time in milliseconds for the Host Controller to retry a
NAK transaction. This register can be used in combination with
HcATLPTDDoneThresholdCount.
HcATLPTDDoneThresholdCount register.
Remark: If the time-out indication is not required by software, or there is no active PTD in
the ATL buffer, write 0000h to this register.
Code (Hex): 52 — read
Code (Hex): D2 — write
Bit
15 to 5 -
4 to 0
reserved
R/W
14
14
6
6
0
-
-
-
-
-
-
Symbol
PTDDoneCount
[4:0]
R/W
13
13
5
5
0
-
-
-
-
-
-
Rev. 05 — 8 May 2007
Description
reserved
Number of PTDs to be processed by the Host Controller to generate an
ATL interrupt.
PTDDoneTimeOut[7:0]
R/W
R/W
12
12
4
0
4
0
-
-
-
-
Table 106
reserved
reserved
Table 104
R/W
R/W
shows the bit allocation of the
11
11
3
0
3
0
-
-
-
-
shows the bit allocation of the register.
PTDDoneCount[4:0]
Single-chip USB OTG Controller
R/W
R/W
10
10
2
0
2
0
-
-
-
-
R/W
R/W
9
1
0
9
1
0
-
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1362
105 of 152
R/W
R/W
8
0
1
8
0
1
-
-
-
-