ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 95

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 73.
ISP1362_5
Product data sheet
Bit
15 to 0
HcChipID register: bit description
Symbol
CHIPID[15:0]
14.5.1 HcChipID register (R: 27h)
14.5.2 HcScratch register (R/W: 28h/A8h)
14.5 HC miscellaneous registers
Table 72.
This register contains the ID of the ISP1362. The upper byte identifies the product name
(here 36h stands for the ISP1362). The lower byte indicates the revision number of the
product, including engineering samples.
register.
Code (Hex): 27 — read only
This register is for the HCD to save and restore values when required. The bit description
is given in
Code (Hex): 28 — read
Code (Hex): A8 — write
Bit
15 to 10 -
9
8
7
6
5
4
3
2
1
0
Access
R
Symbol
OTG_IRQ_InterruptEnable 0 — power-up value
ATL_IRQ_InterruptEnable
INTL_IRQ_InterruptEnable 0 — power-up value
ClkReady
HCSuspendedEnable
OPRInterruptEnable
EOTInterruptEnable
ISTL1InterruptEnable
ISTL0InterruptEnable
SOFInterruptEnable
Table
Hc PInterruptEnable register: bit description
74.
Value
3630h
Rev. 05 — 8 May 2007
Description
chip ID of the ISP1362.
Description
reserved
1 — enables the OTG_IRQ interrupt
0 — power-up value
1 — enables the ATL_IRQ interrupt
1 — enables the INT_IRQ interrupt
0 — power-up value
1 — enables the ClkReady interrupt
0 — power-up value
1 — enables the Host Controller suspended interrupt
0 — power-up value
1 — enables the 32-bit operational register’s interrupt
0 — power-up value
1 — enables the EOT interrupt
0 — power-up value
1 — enables the ISTL1 interrupt
0 — power-up value
1 — enables the ISTL0 interrupt
0 — power-up value
1 — enables the SOF interrupt
Table 73
contains the bit description of the
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
ISP1362
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