DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet
DS21Q42T+
Specifications of DS21Q42T+
Related parts for DS21Q42T+
DS21Q42T+ Summary of contents
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FEATURES § Four T1 DS1/ISDN-PRI/J1 framing transceivers § All four framers are fully independent § Each of the four framers contain dual two- frame elastic-store slip buffers that can connect to asynchronous backplanes up to 8.192MHz § 8-bit parallel ...
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INTRODUCTION The DS21Q42 is a superset version of the popular DS21Q41 quad T1 framer offering the new features listed below. All of the original features of the DS21Q41 have been retained and software created for the original device is ...
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FUNCTIONAL DESCRIPTION The receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store can be enabled ...
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Figure 1-1. DS21Q42 ENHANCED QUAD T1 FRAMER 4 of 116 ...
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INTRODUCTION ..............................................................................................................................2 2. DS21Q42 PIN DESCRIPTION .........................................................................................................8 3. DS21Q42 PIN FUNCTION DESCRIPTION .................................................................................15 4. DS21Q42 REGISTER MAP .............................................................................................................22 5. PARALLEL PORT ...........................................................................................................................26 6. CONTROL, ID, AND TEST REGISTERS.....................................................................................26 7. STATUS AND INFORMATION REGISTERS .............................................................................37 8. ERROR COUNT REGISTERS........................................................................................................45 9. ...
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HDLC CONTROLLER ...................................................................................................................59 14.1. HDLC FOR DS0S ....................................................................................................................59 15. FDL/FS EXTRACTION AND INSERTION ..................................................................................60 15.1. HDLC AND BOC CONTROLLER FOR THE FDL ..............................................................60 15.1.1. General Overview ...........................................................................................................60 15.1.2. Status Register for the HDLC .........................................................................................61 15.1.3. HDLC/BOC Register Description ..................................................................................63 ...
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DOCUMENT REVISION HISTORY REVISION NOTES: DATE 122298 Initial Release § Changed explanation on JTRST test access port pin § All instances of JTRST* changed to JTRST 051900 § Corrected errors in the JTAG portion of data sheet § Updated device ...
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DS21Q42 PIN DESCRIPTION Table 2-1. PIN DESCRIPTION SORTED BY PIN NUMBER PIN SYMBOL 1 TCHBLK0 2 TPOS0 3 TNEG0 4 RLINK0 5 RLCLK0 6 RCLK0 7 RNEG0 8 RPOS0 9 RSIG0 [RCHCLK0] 10 RCHBLK0 11 RSYSCLK0 12 RSYNC0 13 ...
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PIN SYMBOL 39 RLCLK1 40 RCLK1 41 RNEG1 42 RPOS1 43 RSIG1 [RCHCLK1] 44 RCHBLK1 45 RSYSCLK1 FMS 48 RSYNC1 49 RSER1 50 JTMS [RMSYNC1] 51 RFSYNC1 52 JTCLK [RLOS/LOTC1] 53 TCLK1 54 TLCLK1 55 TSYNC1 56 ...
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PIN SYMBOL 81 RSYSCLK2 82 RSYNC2 83 RSER2 84 JTDI [RMSYNC2] 85 RFSYNC2 86 JTDO [RLOS/LOTC2] 87 TCLK2 88 TLCLK2 89 TSYNC2 90 TLINK2 91 TSYSCLK3 92 TSER3 93 TSSYNC3 94 TSIG3 [TCHCLK3] 95 TCHBLK3 96 TPOS3 97 TNEG3 98 ...
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PIN SYMBOL 122 D5 or AD5 123 D6 or AD6 124 D7 or AD7 125 TSYSCLK0 126 TSER0 127 TSSYNC0 128 TSIG0 [TCHCLK0] NOTE: 1) Brackets [ ] indicate pin function when the DS21Q42 is configured for emulation of the ...
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Table 2-2. PIN DESCRIPTION SORTED BY PIN FUNCTION, FMS = 0 PIN SYMBOL 108 8MCLK A6/ALE (AS BTS 112 CLKSI 60 CS* 117 D0 ...
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PIN SYMBOL 39 RLCLK1 73 RLCLK2 99 RLCLK3 4 RLINK0 38 RLINK1 72 RLINK2 98 RLINK3 7 RNEG0 41 RNEG1 75 RNEG2 101 RNEG3 8 RPOS0 42 RPOS1 76 RPOS2 102 RPOS3 13 RSER0 49 RSER1 83 RSER2 107 RSER3 ...
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PIN SYMBOL 90 TLINK2 116 TLINK3 3 TNEG0 37 TNEG1 71 TNEG2 97 TNEG3 2 TPOS0 36 TPOS1 70 TPOS2 96 TPOS3 126 TSER0 32 TSER1 66 TSER2 92 TSER3 128 TSIG0 34 TSIG1 68 TSIG2 94 TSIG3 127 TSSYNC0 ...
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DS21Q42 PIN FUNCTION DESCRIPTION TRANSMIT SIDE PINS Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data ...
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Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs–bit position (D4) ...
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RECEIVE SIDE PINS Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with either FDL data (ESF bits (D4 bits (ZBTSI) one RCLK before the start of a frame. See Section 20 for ...
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Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will output multiframe ...
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Signal Name: RNEG Signal Description: Receive Negative Data Input Signal Type: Input Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and RNEG can be tied together for an NRZ interface. ...
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Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = ...
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Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. This pin ...
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DS21Q42 REGISTER MAP Table 4-1. REGISTER MAP SORTED BY ADDRESS ADDRESS R/W 00 R/W HDLC Control 01 R/W HDLC Status 02 R/W HDLC Interrupt Mask 03 R/W Receive HDLC Information 04 R/W Receive Bit Oriented Code 05 R Receive ...
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ADDRESS R/W 2A R/W Receive FDL Match 2 2B R/W Receive Control 1 2C R/W Receive Control 2 2D R/W Receive Mark 1 2E R/W Receive Mark 2 2F R/W Receive Mark 3 30 R/W Common Control 3 31 R/W ...
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ADDRESS R/W 58 R/W Receive Channel 17 59 R/W Receive Channel 18 5A R/W Receive Channel 19 5B R/W Receive Channel 20 5C R/W Receive Channel 21 5D R/W Receive Channel 22 5E R/W Receive Channel 23 5F R/W Receive ...
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ADDRESS R/W 86 R/W Receive Channel 7 87 R/W Receive Channel 8 88 R/W Receive Channel 9 89 R/W Receive Channel 10 8A R/W Receive Channel 11 8B R/W Receive Channel 12 8C R/W Receive Channel 13 8D R/W Receive ...
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PARALLEL PORT The DS21Q42 is controlled via either a nonmultiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21Q42 can operate with either Intel or Motorola bus timing configurations. If ...
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IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex) (MSB) T1E1 0 SYMBOL POSITION T1E1 IDR.7 ID3 IDR.3 ID2 IDR.1 ID1 IDR.2 ID0 IDR.0 RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex) (MSB) LCVCRF ARC SYMBOL POSITION LCVCRF RCR1.7 ARC RCR1.6 OOF1 RCR1.5 OOF2 ...
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SYMBOL POSITION SYNCE RCR1.1 RESYNC RCR1.0 RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex) (MSB) RCS RZBTSI RSDW SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 NAME AND DESCRIPTION Sync Enable. ...
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex) (MSB) LOTCMC TFPT SYMBOL POSITION LOTCMC TCR1.7 TFPT TCR1.6 TCPT TCR1.5 TSSE TCR1.4 GB7S TCR1.3 TFDLS TCR1.2 TBL TCR1.1 TYEL TCR1.0 NOTE: For a description of how the bits in TCR1 affect the ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex) (MSB) TEST1 TEST0 TZBTSI SYMBOL POSITION TEST1 TCR2.7 TEST0 TCR2.6 TZBTSI TCR2.5 TSDW TCR2.4 TSM TCR2.3 TSIO TCR2.2 TD4YM TCR2.1 TB7ZS TCR2.0 Table 6-1. OUTPUT PIN TEST MODES TEST 1 TEST 0 0 ...
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CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex) (MSB) TESE ODF RSAO SYMBOL POSITION TESE CCR1.7 ODF CCR1.6 RSAO CCR1.5 TSCLKM CCR1.4 RSCLKM CCR1.3 RESE CCR1.2 PLB CCR1.1 FLB CCR1.0 Payload Loopback When CCR1.1 is set to a one, the DS21Q42 ...
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Framer Loopback When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit side back to ...
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CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex) (MSB) RESMDM TCLKSRC RLOSF SYMBOL POSITION RESMDM CCR3.7 TCLKSRC CCR3.6 RLOSF CCR3.5 RSMS CCR3.4 PDE CCR3.3 ECUS CCR3.2 TLOOP CCR3.1 TESMDM CCR3.0 RSMS PDE NAME AND DESCRIPTION Receive Elastic Store Minimum Delay Mode. ...
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Pulse Density Enforcer The Framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: – No more than 15 consecutive zeros – At least N ones in each ...
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SYMBOL POSITION THSE CCR4.2 TPCSI CCR4.1 TIRFS CCR4.0 CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex) (MSB) TJC – SYMBOL POSITION TJC CCR5.7 – CCR5.6 – CCR5.5 TCM4 CCR5.4 TCM3 CCR5.3 TCM2 CCR5.2 TCM1 CCR5.1 TCM0 CCR5.0 NAME AND DESCRIPTION Transmit ...
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CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) (MSB) RJC RESALGN TESALGN SYMBOL POSITION RJC CCR6.7 RESALGN CCR6.6 TESALGN CCR6.5 RCM4 CCR6.4 RCM3 CCR6.3 RCM2 CCR6.2 RCM1 CCR6.1 RCM0 CCR6.0 RCM4 RCM3 RCM2 NAME AND DESCRIPTION Receive Japanese CRC6 Enable. 0 ...
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CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex) (MSB) - RLB SYMBOL POSITION – CCR7.7 RLB CCR7.6 RESR CCR7.5 TESR CCR7.4 – CCR7.3 – CCR7.2 – CCR7.1 – CCR7.0 Remote Loopback When CCR7.6 is set to a one, the DS21Q42 will ...
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The user will always precede a read of any of the nine registers with a write. The byte written to the register will inform the DS21Q42 which bits the user wishes to read and have cleared. The user will write ...
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SYMBOL POSITION F2SR ISR.4 F1HDLC ISR.3 F1SR ISR.2 F0HDLC ISR.1 F0SR ISR RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex) (MSB) COFA 8ZD SYMBOL POSITION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 ...
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RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex) (MSB) RLOSC RCLC SYMBOL POSITION RLOSC RIR2.7 RCLC RIR2.6 TESF RIR2.5 TESE RIR2.4 TSLIP RIR2.3 RBLC RIR2.2 RPDV RIR2.1 TPDV RIR2.0 RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex) (MSB SYMBOL POSITION ...
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SR1: STATUS REGISTER 1 (Address=20 Hex) (MSB) LUP LDN LOTC SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 RCL SR1.1 RLOS SR1.0 RSLIP RBL RYEL NAME AND DESCRIPTION Loop Up Code Detected. Set when ...
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Table 7-1. ALARM CRITERIA ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm (RAI bit 2 mode(RCR2.2= 12th F–bit mode (RCR2.2=1; this mode is also referred to as the “Japanese Yellow Alarm”) 3. ESF mode ...
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SR2: STATUS REGISTER 2 (Address=21 Hex) (MSB) RMF TMF SYMBOL POSITION RMF SR2.7 TMF SR2.6 SEC SR2.5 RFDL SR2.4 TFDL SR2.3 RMTCH SR2.2 RAF SR2.1 RSC SR2.0 IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex) (MSB) (LSB) LUP LDN LOTC SYMBOL ...
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SYMBOL POSITION RCL IMR1.1 RLOS IMR1.0 IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex) (MSB) (LSB) RMF TMF SYMBOL POSITION RMF IMR2.7 TMF IMR2.6 SEC IMR2.5 RFDL IMR2.4 TFDL IMR2.3 RMTCH IMR2.2 RAF IMR2.1 RSC IMR2.0 NAME AND DESCRIPTION Receive Carrier ...
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ERROR COUNT REGISTERS There are a set of three counters in each framer that record bipolar violations, excessive zeros, errors in the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive ...
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Path Code Violation Count Register (PCVCR) When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12–bit counter that will record errors in the CRC6 code ...
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MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR) Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss ...
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Table 8-3. MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS FRAMING MODE COUNT MOS OR F-BIT (CCR2.3) ERRORS (RCR2. ESF ESF 9. DS0 MONITORING FUNCTION Each framer in the DS21Q42 has the ability to monitor one DS0 64 kbps channel ...
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B1 B2 SYMBOL POSITION B1 TDS0M.7 B2 TDS0M.6 B3 TDS0M.5 B4 TDS0M.4 B5 TDS0M.3 B6 TDS0M.2 B7 TDS0M.1 B8 TDS0M.0 CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) [repeated here from section 6 for convenience] (MSB) RJC RESALGN TESALGN SYMBOL ...
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SYMBOL POSITION RCM3 CCR6.3 RCM2 CCR6.2 RCM1 CCR6.1 RCM0 CCR6.0 RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex) (MSB SYMBOL POSITION B1 RDS0M.7 B2 RDS0M.6 B3 RDS0M.5 B4 RDS0M.4 B5 RDS0M.3 B6 RDS0M.2 B7 RDS0M.1 B8 RDS0M.0 10. SIGNALING ...
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RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address= Hex) (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(24) A/C(23) A/C(22) B/D(8) B/D(7) ...
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TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address= Hex) (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9) ...
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The other hardware based signaling operating mode called signaling re–insertion can be invoked by setting the RSRE control bit high (CCR4.7=1). In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will ...
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Simple Idle Code Insertion and Per-Channel Loopback The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). ...
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Per-Channel Code Insertion The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine which of the 24 T1 channels should be overwritten with the code placed in the Transmit Channel Registers (TC1 to TC24). This method ...
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RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address= Hex) (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 SYMBOLS POSITIONS CH1 – 24 RMR1.0 - 3.7 11.2.2 Per-Channel Code Insertion The second method involves using the Receive Channel Control Registers ...
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CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low ...
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ELASTIC STORES OPERATION Each framer in the DS21Q42 contains dual two–frame (386 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to ...
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Minimum Delay Synchronous RSYSCLK/TSYSCLK Mode In applications where the framer is connected to backplanes that are frequency locked to the recovered T1 clock (i.e., the RCLK output), the full two frame depth of the onboard elastic stores is really ...
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Transmit a HDLC Message 1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register. 2) Enable either ...
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Table 15-1. HDLC/BOC CONTROLLER REGISTER LIST NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HDLC Interrupt Mask Register (HIMR) Receive HDLC Information Register (RHIR) Receive BOC Register (RBOC) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 ...
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Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt ...
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Transmit a HDLC Message 1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register. 2) Enable either ...
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SYMBOL POSITION TZSD HCR.1 TCRCD HCR.0 HSR: HDLC STATUS REGISTER (Address = 01 Hex) (MSB) RBOC RPE SYMBOL POSITION RBOC HSR.7 RPE HSR.6 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 Note: The RBOC, RPE, RPS, ...
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HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex) (MSB) RBOC RPE SYMBOL POSITION RBOC HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 TMEND HIMR.0 RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = 03 Hex) (MSB) ...
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SYMBOL POSITION POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 Note: The RABT, RCRCE, ROVR, and RVM bits are latched and are cleared when read. RBOC: RECEIVE BIT ORIENTED CODE REGISTER (Address = 04 Hex) (MSB) LBD BD BOC5 SYMBOL POSITION LBD ...
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RHFR: RECEIVE HDLC FIFO (Address = 05 Hex) (MSB) HDLC7 HDLC6 HDLC5 SYMBOL POSITION HDLC7 RHFR.7 HDLC6 RHFR.6 HDLC5 RHFR.5 HDLC4 RHFR.4 HDLC3 RHFR.3 HDLC2 RHFR.2 HDLC1 RHFR.1 HDLC0 RHFR.0 THIR: TRANSMIT HDLC INFORMATION (Address = 06 Hex) (MSB) – ...
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TBOC: TRANSMIT BIT ORIENTED CODE (Address = 07 Hex) (MSB) SBOC HBEN SYMBOL POSITION SBOC TBOC.7 HBEN TBOC.6 BOC5 TBOC.5 BOC4 TBOC.4 BOC3 TBOC.3 BOC2 TBOC.2 BOC1 TBOC.1 BOC0 TBOC.0 THFR: TRANSMIT HDLC FIFO (Address = 08 Hex) (MSB) HDLC7 ...
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RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = 90 Hex) (MSB) RDS0E - RDS0M SYMBOL POSITION RDS0E RDC1.7 - RDC1.6 RDS0M RDC1.5 RD4 RDC1.4 RD3 RDC1.3 RD2 RDC1.2 RD1 RDC1.1 RD0 RDC1.0 RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 ...
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = 92 Hex) (MSB) TDS0E - TDS0M SYMBOL POSITION TDS0E TDC1.7 - TDC1.6 TDS0M TDC1.5 TD4 TDC1.4 TD3 TDC1.3 TD2 TDC1.2 TD1 TDC1.1 TD0 TDC1.0 TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 ...
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Legacy FDL Support 15.2.1 Overview The DS21Q42 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s single chip transceivers and quad framers. Section 15.2 covers the circuitry and operation of this legacy functionality. In new applications, ...
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RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex) RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex) (MSB) RMFDL7 RMFDL6 RMFDL5 SYMBOL POSITION RMFDL7 RMTCH1.7 RMTCH2.7 RMFDL0 RMTCH1.0 RMTCH2.0 When the byte in the Receive FDL Register ...
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D4/SLC–96 OPERATION In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed ...
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Table 16-1. TC1 TC0 Table 16-2. RECEIVE CODE LENGTH RUP2/RDN2 RUP1/RDN1 TCD: TRANSMIT CODE DEFINITION REGISTER ...
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RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex) (MSB SYMBOL POSITION C7 RUPCD.7 C6 RUPCD.6 C5 RUPCD.5 C4 RUPCD.4 C3 RUPCD.3 C2 RUPCD.2 C1 RUPCD.1 C0 RUPCD.0 RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex) (MSB ...
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TRANSMIT TRANSPARENCY Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting ...
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For all bus configurations, one framer will be configured as the master device and the remaining framers on the shared bus will be configured as slave devices. Refer to the IBO register description below for more detail. In the 4.096 ...
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Figure 18-1. 4.096MHz INTERLEAVED BUS EXTERNAL PIN CONNECTION EXAMPLE FRAMER 0 FRAMER 1 RSYSCLK0 RSYSCLK1 TSYSCLK0 TSYSCLK1 RSYNC0 RSYNC1 TSSYNC0 TSSYNC1 RSER0 RSER1 TSER0 TSER1 RSIG0 RSIG1 TSIG0 TSIG1 Bus 1 Figure 18-2. 8.192MHz INTERLEAVED BUS EXTERNAL PIN CONNECTION EXAMPLE ...
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JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 19.1 Description The DS21Q42 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP, and IDCODE. See Figure 19-1 for ...
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TAP Controller State Machine This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. Please see Figure 19.2 for details on each of the states described below. TAP Controller The TAP controller ...
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Exit2-DR While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the Shift- DR state. ...
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Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on ...
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Table 19-1. INSTRUCTION CODES FOR THE DS21352/552 IEEE 1149.1 ARCHITECTURE INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SAMPLE/PRELOAD A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the DS21Q42 can be sampled ...
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Table 19-3. DEVICE ID CODES DEVICE 16-BIT NUMBER DS21Q42 DS21Q44 HIGH-Z All digital outputs of the DS21Q42 will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. CLAMP All digital outputs of ...
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Table 19-4. BOUNDARY SCAN REGISTER DESCRIPTION SCAN PIN REGISTER BIT — — ...
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SCAN PIN REGISTER BIT — — ...
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SCAN PIN REGISTER BIT — — — 87 125 88 124 — 123 89 122 90 121 91 120 92 119 93 118 94 117 95 116 96 115 97 114 ...
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SCAN PIN REGISTER BIT 118 92 119 91 120 90 121 89 122 88 123 87 124 86 125 85 126 84 127 83 128 82 20. TIMING DIAGRAMS Figure 20-1. RECEIVE SIDE D4 TIMING NOTES: 1) RSYNC in the ...
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Figure 20-2. RECEIVE SIDE ESF TIMING NOTES: 1) RSYNC in the frame mode (RCR2 and double-wide frame sync is not enabled (RCR2.5 = 0). 2) RSYNC in the frame mode (RCR2 and double-wide frame sync is ...
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Figure 20-3. RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) NOTES: 1) There RCLK delay from RPOS/RNEG to RSER. 2) RCHBLK is programmed to block channel 24. 3) Shown is RLINK/RLCLK in the ESF framing mode. 90 ...
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Figure 20-4. RECEIVE SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled) NOTES: 1) RSYNC is in the output mode (RCR2.3 = 0). 2) RSYNC is in the input mode (RCR2.3 = 1). 3) RCHBLK is programmed to block channel 24. ...
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Figure 20-5. RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) NOTES: 1) RSER data in channels 13, 17, 21, 25, and 29 are forced RSYNC is in the output mode (RCR2.3 = 0). ...
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Figure 20-6. RECEIVE SIDE, INTERLEAVED BUS OPERATION BYTE MODE TIMING NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) RSYNC is in the input mode (RCR2 116 ...
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Figure 20-7. RECEIVE SIDE, INTERLEAVED BUS OPERATION FRAME MODE TIMING NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) RSYNC is in the input mode (RCR2 116 ...
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Figure 20-8. TRANSMIT SIDE D4 TIMING NOTES: 1) TSYNC in the frame mode (TCR2 and double-wide frame sync is not enabled (TCR2.4 = 0). 2) TSYNC in the frame mode (TCR2 and double-wide frame sync is ...
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Figure 20-9. TRANSMIT SIDE ESF TIMING NOTES: 1) TSYNC in the frame mode (TCR2 and double-wide frame sync is not enabled (TCR2.4 = 0). 2) TSYNC in the frame mode (TCR2 and double-wide frame sync is ...
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Figure 20-10. TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) NOTES: 1) There TCLK delay from TSER to TPOS/TNEG. 2) TSYNC is in the output mode (TCR2.2 = 1). 3) TSYNC is in the input mode (TCR2.2 ...
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Figure 20-11. TRANSMIT SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled) NOTES: 1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during channel 24 ...
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Figure 20-12. TRANSMIT SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) NOTES: 1) TSER data in channels 13, 17, 21, 25, and 29 is ignored. 2) TCHBLK is programmed to block channel 31 (if the TPCSI bit ...
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Figure 20-13. TRANSMIT SIDE, INTERLEAVED BUS OPERATION BYTE MODE TIMING NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 100 of 116 ...
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Figure 20-14. TRANSMIT SIDE, INTERLEAVED BUS OPERATION FRAME MODE TIMING NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 101 of 116 ...
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Figure 20-15. DS21Q42 TRANSMIT DATA FLOW NOTES: 1) TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly sourced from RSER. 102 of 116 ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage Range on any Non-Supply Pin Relative to Ground Supply Voltage Range Operating Temperature Range for DS21Q42T Operating Temperature Range for DS21Q42TN Storage Temperature Range *This is a stress rating only and functional operation ...
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AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (MUX = 1) PARAMETER SYMBOL Cycle Time Pulse Width, DS low or RD*high Pulse Width, DS high or RD* low Input Rise/Fall times R/W* Hold Time R/W* Setup time before DS high CS*, FSO or FS1 ...
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AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (MUX = 0) PARAMETER SYMBOL Setup Time for A0 to A7, FS0 or FS1 Valid to CS*Active Setup Time for CS* Active to either RD*, WR*, or DS* Active Delay Time from either RD* or DS* ...
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AC CHARACTERISTICS—RECEIVE SIDE PARAMETER SYMBOL RCLK Period RCLK Pulse Width RSYSCLK Period RSYSCLK Pulse Width RSYNC Setup to RSYSCLK Falling RSYNC Pulse Width RPOS/RNEG Setup to RCLK Falling RPOS/RNEG Hold From RCLK Falling RSYSCLK/RCLK Rise and Fall Times Delay RCLK ...
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AC CHARACTERISTICS—RANSMIT SIDE PARAMETER SYMBOL TCLK Period TCLK Pulse Width TCLKI Pulse Width TSYSCLK Period TSYSCLK Pulse Width TSYNC or TSSYNC Setup to TCLK or TSYSCLK falling TSYNC or TSSYNC Pulse Width TSER, TSIG, TLINK Setup to TCLK, TSYSCLK Falling ...
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Figure 21-1. INTEL BUS READ AC TIMING (BTS = 0 / MUX = 1) Figure 21-2. INTEL BUS WRITE TIMING (BTS = 0 / MUX = 1) 108 of 116 ...
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Figure 21-3. MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 21-4. INTEL BUS READ AC TIMING (BTS = 0 / MUX = 0) 109 of 116 ...
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Figure 21-5. INTEL BUS WRITE AC TIMING (BTS = 0 / MUX = 0) Figure 21-6. MOTOROLA BUS READ AC TIMING (BTS = 1 / MUX = 0) NOTES: 1) The signal DS is active high when emulating the DS21Q41 ...
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Figure 21-7. MOTOROLA BUS WRITE AC TIMING (BTS = 1 / MUX = 0) NOTES: 1) The signal DS is active high when emulating the DS21Q41 (FMS = 1). 111 of 116 ...
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Figure 21-8. RECEIVE SIDE AC TIMING NOTES: 1) RSYNC is in the output mode (RCR2.3 = 0). 2) Shown is RLINK/RLCLK in the ESF framing mode relationship between RCHCLK and RCHBLK and the other signals is implied. 112 ...
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Figure 21-9. RECEIVE SYSTEM SIDE AC TIMING NOTES: 1) RSYNC is in the output mode (RCR2 RSYNC is in the input mode (RCR2 113 of 116 ...
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Figure 21-10. RECEIVE LINE INTERFACE AC TIMING Figure 21-11. TRANSMIT SIDE AC TIMING NOTES: 1) TSYNC is in the output mode (TCR2.2 = 1). 2) TSYNC is in the input mode (TCR2.2 = 0). 3) TSER is sampled on the ...
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Figure 21-12. TRANSMIT SYSTEM SIDE AC TIMING NOTES: 1) TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic ...
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TQFP PACKAGE SPECIFICATIONS 116 of 116 ...