DS21Q42T+ Maxim Integrated Products, DS21Q42T+ Datasheet - Page 49

• Manufacturer Part Number: DS21Q42T+
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T+

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from section 6 for convenience]
(MSB)
RJC
(MSB)
B1
RESALGN
TESALGN
SYMBOL
SYMBOL
RCM4
RJC
B1
B2
B3
B4
B5
B6
B7
B8
RESALGN
B2
POSITION
POSITION
TDS0M.7
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
TDS0M.1
TDS0M.0
TESALGN
CCR6.7
CCR6.6
CCR6.5
CCR6.4
B3
RCM4
NAME AND DESCRIPTION
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be transmitted).
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
NAME AND DESCRIPTION
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Receive Elastic Store Align. Setting this bit from a zero to a
one will force the receive elastic store’s write/read pointers to
a minim separation of half a frame. If pointer separation is
already greater than half a frame, setting this bit will have no
effect. Should be toggled after RSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 13 for details.
Transmit Elastic Store Align. Setting this bit from a zero to
a one will force the transmit elastic store’s write/read pointers
to a minimum separation of half a frame. If pointer separation
is already greater than half a frame, setting this bit will have no
effect. Should be toggled after TSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 13 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
B4
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RCM3
B5
RCM2
B6
RCM1
B7
(LSB)
RCM0
LSB)
B8