ISP1181BDGG ST-Ericsson Inc, ISP1181BDGG Datasheet - Page 32
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ISP1181BDGG
Manufacturer Part Number
ISP1181BDGG
Description
IC USB CNTRLR FULL-SPD 48-TSSOP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1181BBSUM.pdf
(71 pages)
Specifications of ISP1181BDGG
Controller Type
USB Peripheral Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
26mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1002-5
ISP1181BDGG,112
ISP1181BDGG,112
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Philips Semiconductors
Table 26:
9397 750 13958
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Counter Register: bit allocation
R/W
R/W
15
0
7
0
12.1.7 Write/Read DMA Counter
Table 25:
This command accesses the DMA Counter Register, which consists of 2 bytes. The
bit allocation is given in
DMA transfer. Reading the register returns the number of remaining bytes in the
current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter Register
when DMA is re-enabled (DMAEN = 1). See
Code (Hex): F2/F3 — write/read DMA Counter Register
Transaction — write/read 2 bytes
Bit
15
14
13 to 8
7 to 4
3
2
1 to 0
R/W
R/W
14
0
6
0
DMA Configuration Register: bit description
Symbol
CNTREN
SHORTP
-
EPDIX[3:0]
DMAEN
-
BURSTL[1:0]
R/W
R/W
13
0
5
0
Rev. 02 — 07 December 2004
Table
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) this bit should be
cleared. Bus reset value: unchanged.
reserved
Indicates the destination endpoint for DMA, see
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit
is cleared by a bus reset.
reserved
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
R/W
R/W
12
0
4
0
DMACRH[7:0]
DMACRL[7:0]
26. Writing to the register sets the number of bytes for a
R/W
R/W
11
0
3
0
Section 12.1.6
Full-speed USB peripheral controller
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
for more details.
ISP1181B
R/W
R/W
9
0
1
0
Table
7.
R/W
R/W
8
0
0
0
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