DP8390DV National Semiconductor, DP8390DV Datasheet - Page 14

• Manufacturer Part Number: DP8390DV
• Description: IC CTRLR NETWORK IN (NIC)68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8390DV

• Controller Type: Network Interface Controller (NIC)
• Voltage - Supply: 5V
• Current - Supply: 40mA
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP8390DV

9 0 Remote DMA
2 Issue the ‘‘dummy’’ Remote Read command
3 Read the Current Remote DMA Address (CRDA) (both
4 Compare to previous CRDA value if different go to 6
5 Delay and jump to 3
6 Set up for the Remote Write command by setting the
7 Issue the Remote Write command
FIFO AND BUS OPERATIONS
Overview
To accommodate the different rates at which data comes
from (or goes to) the network and goes to (or comes from)
the system memory the NIC contains a 16-byte FIFO for
buffering data between the bus and the media The FIFO
threshold is programmable allowing filling (or emptying) the
FIFO at different rates When the FIFO has filled to its pro-
grammed threshold the local DMA channel transfers these
bytes (or words) into local memory It is crucial that the local
DMA is given access to the bus within a minimum bus laten-
cy time otherwise a FIFO underrun (or overrun) occurs
To understand FIFO underruns or overruns there are two
causes which produce this condition
1) the bus latency is so long that the FIFO has filled (or
2) the bus latency or bus data rate has slowed the through-
The worst case condition ultimately limits the overall bus
latency which the NIC can tolerate
FIFO Underrun and Transmit Enable
During transmission if a FIFO underrun occurs the Trans-
mit enable (TXE) output may remain high (active) Generally
this will cause a very large packet to be transmitted onto the
network The jabber feature of the transceiver will terminate
the transmission and reset TXE
To prevent this problem a properly designed system will not
allow FIFO underruns by giving the NIC a bus acknowledge
within time shown in the maximum bus latency curves
shown and described later
FIFO at the Beginning of Receive
At the beginning of reception the NIC stores entire Address
field of each incoming packet in the FIFO to determine
whether the packet matches its Physical Address Registers
or maps to one of its Multicast Registers This causes the
FIFO to accumulate 8 bytes Furthermore there are some
synchronization delays in the DMA PLA Thus the actual
time that BREQ is asserted from the time the Start of Frame
Delimiter (SFD) is detected is 7 8 s This operation affects
the bus latencies at 2 and 4 byte thresholds during the first
receive BREQ since the FIFO must be filled to 8 bytes (4
words) before issuing a BREQ
bytes)
Remote Byte Count and the Remote Start Address (note
that if the Remote Byte count in step 1 can be set to the
tramsmit byte count plus one and the Remote Start Ad-
dress to one less these will now be incremented to the
correct values )
emptied) from the network before the local DMA has
serviced the FIFO
put of the local DMA to point where it is slower than the
network data rate (10 Mb s) This second condition is
also dependent upon DMA clock and word width (byte
wide or word wide)
(Continued)
14
FIFO Operation at the End of Receive
When Carrier Sense goes low the NIC enters its end of
packet processing sequence emptying its FIFO and writing
the status information at the beginning of the packet figure
below This NIC holds onto the bus for the entire sequence
The longest time BREQ may be extended occurs when a
packet ends just as the NIC performs its last FIFO burst
The NIC in this case performs a programmed burst transfer
followed by flushing the remaining bytes in the FIFO and
completes by writing the header information to memory The
following steps occur during this sequence
1) NIC issues BREQ because the FIFO threshold has been
2) During the burst packet ends resulting in BREQ extend-
3) NIC flushes remaining bytes from FIFO
4) NIC performs internal processing to prepare for writing
5) NIC writes 4-byte (2-word) header
6) NIC deasserts BREQ
End of Packet Processing (EOPP) times for 10 MHz and
20 MHz have been tabulated in the table below
Threshold Detection (Bus Latency)
To assure that no overwriting of data in the FIFO the FIFO
logic flags a FIFO overrun as the 13th byte is written into the
FIFO effectively shortening the FIFO to 13 bytes The FIFO
logic also operates differently in Byte Mode and in Word
Mode In Byte Mode a threshold is indicated when the n
Mode
Word
Word
reached
ed
the header
Byte
Byte
End of Packet Processing Times for Various FIFO
Thresholds Bus Clocks and Transfer Modes
Threshold
2 bytes
4 bytes
8 bytes
2 bytes
4 bytes
8 bytes
2 bytes
4 bytes
8 bytes
2 bytes
4 bytes
8 bytes
End of Packet Processing
Bus Clock
10 MHz
20 MHz
10 MHz
20 MHz
11 0 s
7 0 s
8 6 s
3 6 s
4 2 s
5 0 s
5 4 s
6 2 s
7 4 s
3 0 s
3 2 s
3 6 s
EOPP
TL F 8582– 97
a
1