DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 11

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

DP8419 Mode Descriptions
MODE 1–AUTOMATIC FORCED REFRESH
In Mode 1 the R C (RFCK) pin becomes RFCK (refresh
cycle clock) and the CASIN (RGCK) pin becomes RGCK
(RAS generator clock) If RFCK is high and Mode 1 is en-
tered then the chip operates as if in MODE 0 (externally
controlled refresh) with all RAS outputs following RASIN
This feature of Mode 1 may be useful for those who want to
use Mode 5 (automatic access) with externally controlled
refresh By holding RFCK permanently high one need only
toggle M2 (RFSH) to switch from Mode 5 to external re-
fresh As with Mode 0 RFI O may be pulled low by an ex-
ternal gate to reset the refresh counter
When using Mode 1 as automatic refresh RFCK must be an
input clock signal One refresh should occur each period of
RFCK If no refresh is performed while RFCK is high then
when RFCK goes low RFI O immediately goes low to indi-
cate that a refresh is requested (RFI O may still be used to
reset the refresh counter even though it is also used as a
refresh request pin however an open-collector gate should
FIGURE 3 DP8419 Performing a Forced Refresh (Mode 5
j
k
l
m
RFCK goes low
RFRQ goes low if no hidden refresh
occurred while RFCK was high
Next RASIN starts next access
P acknowledges refresh request
(Continued)
11
n
o
p
Forced refresh RAS starts after
(
Forced refresh RAS ends RFRQ
l
P removes refresh acknowledge
be used to reset the counter in this case since RFI O is
forced low internally for a request)
After receiving the refresh request the system must allow a
forced refresh to take place while RFCK is low External
logic can monitor RFRQ (RFI O) so that when RFRQ goes
low this logic will wait for the access currently in progress to
be completed before pulling M2 (RFSH) low to put the
DP8419 in mode 1 If no access is taking place when RFRQ
occurs then M2 may immediately go low Once M2 is low
the refresh counter contents appear at the address outputs
and RAS is generated to perform the refresh
An external clock on RGCK is required to derive the refresh
RAS signals On the second falling edge of RGCK after M2
is low all RAS lines go low They remain low until two more
falling edges of RGCK Thus RAS remains high for one to
two periods of RGCK after M2 goes low and stays low for
two periods In order to obtain the minimum delay from M2
going low to RAS going low M2 should go low t
fore the falling edge of RGCK
t
RP
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1
5) with Various Microprocessors
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T
TL F 8396 – 11
RFSRG
be-