DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 22

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

ACCESS (Continued)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
REFRESH
t
t
t
Switching Characteristics DP8417 DP8418 DP8419 DP8419X
V
of 22 DRAMs each or 88 DRAMs including trace capacitance
unless otherwise noted See Figure 11a for test load S1 is open unless otherwise specified Maximum propagation
delays are specified with all outputs switching
Symbol
RCV0
RCV0
RCV1
RCV1
RPDL
RPDH
ASRL
APD
SPD
ASA
AHA
ADS
WPD
CPDL
CPDH
CPdif
RCC
RCR
RHA
CCAS
DIF1
DIF2
RC
RASINL H
RFPDL0
CC
These values are Q0-Q8 C
Preliminary
e
5 0V
g
RASIN to Column Address
Valid (RAHS
RASIN to Column Address
Valid (RAHS
RASIN to Column Address
Valid (RAHS
RASIN to Column Address
Valid (RAHS
RASIN to RAS Low Delay
RASIN to RAS High Delay
Address Set-up to RASIN low
Address Input to Output
Delay
Address Strobe High to
Address Output Valid
Address Set-up Time to ADS
Address Hold Time from ADS
Address Strobe Pulse Width
WIN to WE Output Delay
CASIN to CAS Low Delay
(R C low Mode 4)
CASIN to CAS High Delay
(R C low Mode 4)
t
Column Select to Column
Address Valid
Row Select to Row
Address Valid
Row Address Held from
Column Select
R C Low to CAS Low Delay
(CASIN Low Mode 4)
R C Low to CAS Low Delay
(CASIN Low Mode 4)
Maximum (t
Maximum (t
Refresh Cycle Period
Pulse Width of RASIN
during Refresh
RASIN to RAS Low Delay
during Refresh (Mode 0)
10% 0 C
CPDL
- t
CPDH
Parameter
s
RPDL
RCC
T
e
e
e
e
A s
L
0 Mode 5)
0 Mode 5)
1 Mode 5)
1 Mode 5)
- t
- t
e
CPDL
70 C unless otherwise noted (Notes 2 4 5) The output load capacitance is typical for 4 banks
RHA
500 pF RAS0–RAS3 C
)
)
Figure 6
Figure 6
Figure 6
Figure 6
Figures 5a 5b 6
Figures 5a 5b 6
Figures 5a 5b 6
Figures 5a 5b 6
Figures 5a 5b
Figures 5a 5b 6
Figures 5a 5b 6
Figures 5a 5b 6
Figure 5b
Figure 5b
Figure 5b
Figure 5a
Figures 5a 5b
Figure 5a
Figure 5a
Figure 5a
Figure 2a
Figure 2a
Figure 2a
DP8417 18 19-80
DP8417 18 19-70
DP8417 18 19-80
DP8417 18 19-70
See Mode 4
Description
DP8417 18 19-80
DP8417 18 19-70
See Mode 4
Description
Condition
L
e
22
150 pF WE C
Min
100
13
10
26
17
13
50
5
7
CL
L
e
Max
94
85
76
68
21
20
36
48
28
33
33
13
41
45
50
46
13
28
7
500 pF CAS C
Min
All C
L
L
e
(Continued)
e
600 pF RL
50 pF
Max
18
17
25
e
500
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns