DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 6

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

Family Device Differences
DP8417 vs DP8419
The DP8417 is identical to the DP8419 with the exception
that its RAS CAS WE and Q (Multiplexed Address) outputs
are TRI-STATE when CS (Chip Select) is high and the chip
is not in a refresh mode This feature allows access to the
same DRAM array through multiple DRAM Controller Driver
DP8417s All AC specifications are the same as the DP8419
except t
for the DP8419 Separate delay specifications for the TRI-
STATE timing paths are provided in the AC tables of this
data sheet
DP8418 vs DP8419
The DP8418 DYNAMIC RAM CONTROLLER DRIVER is
identical to the DP8419 with the exception of two functional
differences incorporated to improve performance with 32-bit
microprocessors
1) Pin 26 (B1) is used to enable disable a pair of RAS out-
2) The hidden refresh function available on the DP8419 has
DP8419 vs DP8409A
The DP8419 High Speed DRAM Controller Driver combines
the most popular memory control features of the
DP8408A 9A DRAM Controller Driver with the high speed
of bipolar oxide isolation processing
The DP8419 retains the high capacitive-load drive capability
of the DP8408A 9A as well as its most frequently used ac-
cess and refresh modes allowing it to directly replace the
DP8408A 9A in applications using only modes 0 1 4 and 5
Thus the DP8419 will allow most DP8408A 9A users to
directly upgrade their system by replacing their old control-
ler chip with the DP8419
The highest priority of the DP8419 is speed By peforming
the DRAM address multiplexing control signal timing and
high-capacitive drive capability on a single chip propagation
delay skews are minimized Emphasis has been placed on
reducing delay variation over the specified supply and tem-
perature ranges
Except for the following a DP8419 will operate essentially
the same as a DP8409A
1) The DP8419 has significantly faster AC performance
2) The DP8419 can replace the DP8409A in applications
puts and pin 27 (B0 on the DP8419) is a no connect
When B1 is low RAS0 and RAS1 are enabled such that
they both go low during an access When B1 is high
RAS2 and RAS3 are enabled This feature is useful when
driving words to 32 bits or more since each RAS would
be driving only one half of the word By distributing the
load on each RAS line in this way the DP8418 will meet
the same AC specifications driving 2 banks of 32 DRAMs
each as the DP8419 does driving 4 banks of 16 bits each
been disabled in order to reduce the amount of setup
time necessary from CS going low to RASIN going low
during an access of DRAM This parameter called
t
DP8419 The hidden refresh function only allows a very
small increase in system performance at best at micro-
processor frequencies of 10 MHz and above
which use modes 0 1 4 and 5 Modes 2 3 6 and 7 of
the DP8409A are not available on the DP8419
CSRL1
CSRLO
is 5 ns for the DP8418 whereas it is 34 ns for the
which is 34 ns for the DP8417 versus 5 ns
6
3) Pin 4 on the DP8419 is RAHS instead of M1 as on the
4) RFI O does not function as an end-of-count signal in
5) DP8419 address and control outputs do not TRI-STATE
Pin Definitions
V
pins have been assigned to the center of the package to
reduce voltage drops both DC and AC There are two
ground pins to reduce the low level noise The second
ground pin is located two pins from V
capacitors can be inserted directly next to these pins It is
important to adequately decouple this device due to the
high switching currents that will occur when all 9 address
bits change in the same direction simultaneously A recom-
mended solution would be a 1 F multilayer ceramic capaci-
tor in parallel with a low-voltage tantalum capacitor both
connected as close as possible to V
lead inductance See Figure below
R0– R8 Row Address Inputs
C0– C8 Column Address Inputs
Q0– Q8 Multiplexed Address Outputs - This address is
selected from the Row Address Input Latch the Column
Address Input Latch or the Refresh Counter
RASIN Row Address Strobe Input - RASIN directly con-
trols the selected RAS output when in an access mode and
all RAS outputs during hidden or external refresh
R C (RFCK) - In the auto-modes this pin is the external
refresh clock input one refresh cycle should be performed
each clock period In the external access mode it is Row
Column Select Input which enables either the row or column
address input latch onto the output bus
CASIN (RGCK) - In the auto-modes this pin is the RAS
Generator Clock input In external access mode it is the
Column Address Strobe input which controls CAS directly
once columns are enabled on the address outputs
ADS Address (Latch) Strobe Input - Row Address Col-
umn Address and Bank Select Latches are fall-through with
ADS high latching occurs on high-to-low transition of ADS
CS Chip Select Input - When high CS disables all access-
es Refreshing however in both modes 0 and 1 is not af-
fected by this pin
M0 M2 (RFSH) Mode Control Inputs - These pins select
one of the four available operational modes of the DP8419
(see Table III)
RFI O Refresh Input Output - In the auto-modes this pin
is the Refresh Request Output It goes low following RFCK
Capacitor values should be chosen depending on the particular application
CC
DP8409A and allows for two choices of t
Mode 0 on the DP8419 as it does on the DP8409A
when CS is high as on the DP8409A DP8419 control
outputs are active high when CS is high (unless refresh-
ing)
GND GND
b
V
CC
e
5V
g
10% The three supply
CC
CC
and GND to reduce
so that decoupling
RAH
in mode 5
TL F 8396– 4