DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 2

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

General Description
In order to specify each device for ‘‘true’’ worst case operat-
ing conditions all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance The chip’s delay timing logic makes
use of a patented new delay line technique which keeps
A C skew to
temperature range of
DP8418 DP8419 and DP8419X guarantee a maximum
RASIN to CASOUT delay of 80 ns or 70 ns even while driv-
ing a 2 Mbyte memory array with error correction check bits
included Speed selected options of these devices are
shown in the switching characteristics section of this docu-
ment
With its four independent RAS outputs and nine multiplexed
address outputs the DP8419 can support up to four banks
of 16k 64k or 256k DRAMs Two bank select pins B1 and
B0 are decoded to activate one of the RAS signals during
g
3 ns over the full V
Device
DP84300
DP84412
DP84512
DP84322
DP84422
DP84522
DP84432
DP84532
DP8400-2
DP8400-4
DP8402A
b
55 C to
(Continued)
CC
a
125 C The DP8417
Programmable Refresh Timer for DP84xx DRAM Controller
NS32008 16 32 to DP8409A 17 18 19 28 29 Interface
NS32332 to DP8417 18 19 28 29 Interface
68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 8 MHz)
68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 12 5 MHz)
68020 to DP8417 18 19 28 29 Interface
8086 88 186 188 to DP8409A 17 18 19 28 29 Interface
80286 to DP8409A 17 18 19 28 29 Interface
16-bit Expandable Error Checker Corrector
16-bit Expandable Error Checker Corrector
32-bit Error Detector and Corrector (EDAC)
range of
System Companion Components
g
10% and
2
an access leaving the three non-selected banks in the
standby mode (less than one tenth of the operating power)
with data outputs in TRI-STATE
The DP8419 has two mode-select pins allowing for two re-
fresh modes and two access modes Refresh and access
timing may be controlled either externally or automatically
The automatic modes require a minimum of input control
signals
A refresh counter is on-chip and is multiplexed with the row
and column inputs Its contents appear at the address out-
puts of the DP8419 during any refresh and are incremented
at the completion of the refresh Row Column and bank
address latches are also on-chip However if the address
inputs to the DP8419 are valid throughout the duration of
the access these latches may be operated in the fall-
through mode
Function