DP83840AVCE National Semiconductor, DP83840AVCE Datasheet - Page 12

• Manufacturer Part Number: DP83840AVCE
• Description: IC ETHERNET PHYS LAYER 100-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83840AVCE

• Controller Type: Ethernet Controller, 10Base-T
• Interface: IEEE 802.3af
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 335mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83840AVCE

Version A
2.0 Pin Description
2.7 IEEE 1149.1 INTERFACE
The IEEE 1149.1 Standard Test Access Port and Boundary Scan (sometimes referred to as JTAG) interface signals
allow system level boundary scan to be performed. These pins may be left floating when JTAG testing is not required.
TDO
TDI
TRST
TCLK
TMS
Signal Name
I = TTL/CMOS input
Type
O, Z
I
I
I
I
O = TTL/CMOS output
(Continued)
Pin #
50
91
92
93
94
TEST DATA OUTPUT: Serial instruction/test output data for the IEEE 1149.1
scan chain.
If Boundary-Scan is not implemented this pin may be left unconnected (NC).
TEST DATA INPUT: Serial instruction/test input data for the IEEE 1149.1 scan
chain.
TEST RESET: An asynchronous low going pulse will reset and initialize the IEEE
1149.1 test circuitry.
If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since
it has an internal pull-up resistor (10 k ).
TEST CLOCK: Test clock for the IEEE 1149.1 circuitry.
If Boundary-Scan is not implemented this pin may be left unconnected (NC).
TEST MODE SELECT: Control input to the IEEE 1149.1 test circuitry.
If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since
it has an internal pull-up resistor (10 k ).
Z = TRI-STATE output
12
J = IEEE 1149.1 pin
Description
National Semiconductor