DP83840AVCE National Semiconductor, DP83840AVCE Datasheet - Page 5

• Manufacturer Part Number: DP83840AVCE
• Description: IC ETHERNET PHYS LAYER 100-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83840AVCE

• Controller Type: Ethernet Controller, 10Base-T
• Interface: IEEE 802.3af
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 335mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83840AVCE

Version A
2.0 Pin Description
The DP83840A pins are classified into the following interface categories (each interface is described in the sections that
follow):
2.1 MII INTERFACE
MII INTERFACE
100 Mb/s SERIAL PMD INTERFACE
10 Mb/s INTERFACE
CLOCK INTERFACE
DEVICE CONFIGURATION INTERFACE
TX_CLK
TXD[3]
TXD[2]
TXD[1]
TXD[0]
TX_EN
TX_ER
(TXD[4])
MDC
MDIO
Signal Name
I = TTL/CMOS input
I/O, Z, J
Type
O, Z
I, J
I, J
I, J
I,J
O = TTL/CMOS output
Pin #
82
75
76
77
78
74
73
72
67
TRANSMIT CLOCK: Transmit clock output from the DP83840A:
25 MHz nibble transmit clock derived from Clock Generator Module's (CGM) PLL
in 100BASE-TX mode
2.5 MHz transmit clock in 10BASE-T nibble mode
10 MHz transmit clock in 10BASE-T serial mode
TRANSMIT DATA: Transmit data MII input pins that accept nibble data during
normal nibble-wide MII operation at either 2.5 MHz (10BASE-T mode) or 25MHz
(100BASE-X mode)
In 10 Mb/s serial mode, the TXD[0] pin is used as the serial data input pin. TXD[3:1]
are ignored.
TRANSMIT ENABLE: Active high input indicates the presence of valid nibble data
on TXD[3:0] for both 100 Mb/s or 10 Mb/s nibble mode.
In 10 Mb/s serial mode, active high indicates the presence of valid 10 Mb/s data on
TXD[0].
TRANSMIT ERROR: In 100 Mb/s mode, when this signal is high and TX_EN is
active the HALT symbol is substituted for the actual data nibble.
In 10 Mb/s mode, this input is ignored.
In encoder bypass mode (BP_4B5B or BP_ALIGN), TX_ER becomes the TXD [4]
pin, the new MSB for the transmit 5-bit data word.
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management
data input/output serial interface which may be asynchronous to transmit and
receive clocks. The maximum clock rate is 2.5 MHz. There is no minimum clock
rate.
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that
may be sourced by the station management entity or the PHY. This pin requires a
1.5k pullup resistor.
Z = TRI-STATE output
5
LED INTERFACE
IEEE 1149.1 INTERFACE
PHY ADDRESS INTERFACE
MISCELLANEOUS PINS
POWER AND GROUND PINS
SPECIAL CONNECT PINS
J = IEEE 1149.1 pin
Description
National Semiconductor
Subject to change without notice.