DP83840AVCE National Semiconductor, DP83840AVCE Datasheet - Page 43
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DP83840AVCE
Manufacturer Part Number
DP83840AVCE
Description
IC ETHERNET PHYS LAYER 100-PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83840AVCE.pdf
(89 pages)
Specifications of DP83840AVCE
Controller Type
Ethernet Controller, 10Base-T
Interface
IEEE 802.3af
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
335mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83840AVCE
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83840AVCE
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83840AVCE
Manufacturer:
NS/国半
Quantity:
20 000
Version A
4.0 Registers
4.2 BASIC MODE CONTROL REGISTER (BMCR)
Address 00h
Bit
15
14
13
12
11
Auto-Negotiation
Speed Selection
Bit Name
Loopback
Reserved
Enable
Reset
(Continued)
0, RW/SC
Default
0, RW
1, RW
1, RW
0, RW
RESET:
1 = Software Reset
0 = Normal Operation
This bit sets the status and control registers of the PHY to their default
states. Setting this bit will also re-latch in all hardware configuration pin
values. This bit, which is self-clearing, returns a value of one until the
reset process is complete. Software should wait 500 s after device
power on before attempting a software reset. Refer to section 3.10.3 for
further detail.
LOOPBACK:
1 = Loopback Enabled
0 = Normal Operation
The loopback function enables MII transmit data to be routed to the MII
receive data path. When set, this bit enables loopback for either
10BASE-T or 100BASE-X modes of operation.
Setting this bit during 100BASE-TX operation may cause the DP83840A
to enter a 550 s “dead time” before any valid data transmit or receive
operations can commence.
This bit takes priority over the loopback control bits 8 and 9 in the
LBREMR register (address 18h).
SPEED SELECT:
1 = 100 Mb/s
0 = 10 Mb/s
Link speed is selected by this bit or by Auto-Negotiation if bit 12 of this
register is set (in which case, the value of this bit is ignored). The latched-
in state of pins AN0 and AN1 will also effect the state of this bit and take
precedence over the Auto-Negotiation Enable bit 12.
AUTO-NEGOTIATION ENABLE:
1 = Auto-Negotiation Enabled--bits 8 and 13 of this register are ignored
0 = Auto-Negotiation Disabled--bits 8 and 13 determine the link speed
If the PHY is configured for non-Auto-Negotiation upon power-up/reset
and it is then decided that Auto-Negotiation is to be enabled through
software, this bit must first be cleared and then set in order for it to take
effect. This bit is intended only to control the state of Auto-Negotiation
and should not be regarded as status. Refer to section3.9.2 for further
detail.
RESERVED:
Write as 0, read as don’t care.
when this bit is set.
and mode.
43
National Semiconductor
Description