AD9951YSVZ Analog Devices Inc, AD9951YSVZ Datasheet - Page 17

• Manufacturer Part Number: AD9951YSVZ
• Description: IC DDS DAC 14BIT 1.8V 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9951YSVZ

• Resolution (bits): 14 b
• Master Fclk: 400MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Data Rate: 25Mbps
• Rf Ic Case Style: TQFP
• No. Of Pins: 48
• Supply Voltage Range: 1.8V To 3.3V
• Operating Temperature Range: -40°C To +105°C
• Msl: MSL 3 - 168 Hours
• Ic Function: Direct Digital Synthesizer
• Digital Ic Case Style: TQFP
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Termination Type: SMD
• Ic Generic Number: 9951
• Base Number: 9951
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9951/PCB - BOARD EVAL FOR AD9951
• Lead Free Status / Rohs Status: Compliant

Other Register Descriptions
Amplitude Scale Factor (ASF)
The ASF register stores the 2-bit auto ramp rate speed value
and the 14-bit amplitude scale factor used in the output shaped
keying (OSK) operation. In auto OSK operation, ASF <15:14>
tells the OSK block how many amplitude steps to take for each
increment or decrement. ASF<13:0> sets the maximum value
achievable by the OSK internal multiplier. In manual OSK
mode, ASF<15:14> has no effect. ASF <13:0> provide the
output scale factor directly. If the OSK enable bit is cleared,
CFR1<25> = 0, this register has no effect on device operation.
Amplitude Ramp Rate (ARR)
The ARR register stores the 8-bit amplitude ramp rate used in
the auto OSK mode. This register programs the rate at which
the amplitude scale factor counter increments or decrements. If
the OSK is set to manual mode, or if OSK enable is cleared, this
register has no effect on device operation.
Frequency Tuning Word 0 (FTW0)
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role is dependent on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. This offset value is added to the output of the phase
accumulator to offset the current phase of the output signal. The
exact value of phase offset is given by the following formula:
MODES OF OPERATION
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the phase
offset register.
PROGRAMMING AD9951 FEATURES
Phase Offset Control
A 14-bit phase offset (θ) may be added to the output of the phase
accumulator by means of the control registers. This feature
provides the user with two different methods of phase control.
The first method is a static phase adjustment, where a fixed
phase offset is loaded into the appropriate phase offset register
and left unchanged. The result is that the output signal is offset
by a constant angle relative to the nominal signal. This allows
the user to phase align the DDS output with some external
signal, if necessary.





POW
2
14




360

Rev. A | Page 17 of 28
The second method of phase control is where the user regularly
updates the phase offset register via the I/O port. By properly
modifying the phase offset as a function of time, the user can
implement a phase modulated output signal. However, both the
speed of the I/O port and the frequency of SYSCLK limit the
rate at which phase modulation can be performed.
The AD9951 allows for a programmable continuous zeroing of
the phase accumulator as well as a clear and release or auto-
matic zeroing function. Each feature is individually controlled
via the CFR1 bits. CFR1<13> is the automatic clear phase
accumulator bit. CFR1<10> clears the phase accumulator and
holds the value to zero.
Continuous Clear Bit
The continuous clear bit is simply a static control signal that,
when active high, holds the phase accumulator at zero for the
entire time the bit is active. When the bit goes low, inactive, the
phase accumulator is allowed to operate.
Clear and Release Function
When set, the auto-clear phase accumulator clears and releases
the phase accumulator upon receiving an I/O UPDATE. The
automatic clearing function is repeated for every subsequent
I/O UPDATE until the appropriate auto-clear control bit is
cleared.
Shaped On-Off Keying
The shaped on-off keying function of the AD9951 allows the
user to control the ramp-up and ramp-down time of an on-off
emission from the DAC. This function is used in burst transmis-
sions of digital data to reduce the adverse spectral impact of
short, abrupt bursts of data.
Auto and manual shaped on-off keying modes are supported.
The auto mode generates a linear scale factor at a rate deter-
mined by the amplitude ramp rate (ARR) register controlled by
an external pin (OSK). Manual mode allows the user to directly
control the output amplitude by writing the scale factor value
into the amplitude scale factor (ASF) register.
The shaped on-off keying function may be bypassed (disabled)
by clearing the OSK enable bit (CFR1<25> = 0).
The modes are controlled by two bits located in the most signifi-
cant byte of the control function register (CFR). CFR1<25> is
the shaped on-off keying enable bit. When CFR1<25> is set, the
output scaling function is enabled and CFR1<25> bypasses the
function. CFR1<24> is the internal shaped on-off keying active
bit. When CFR1<24> is set, internal shaped on-off keying mode
is active; CFR1<24> is cleared, external shaped on-off keying
mode is active. CFR1<24> is a Don’t Care if the shaped on-off
keying enable bit (CFR1<25>) is cleared. The power up condition
is shaped on-off keying disabled (CFR1<25> = 0). Figure 18
shows the block diagram of the OSK circuitry.
AD9951