AD9951YSVZ Analog Devices Inc, AD9951YSVZ Datasheet - Page 22

• Manufacturer Part Number: AD9951YSVZ
• Description: IC DDS DAC 14BIT 1.8V 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9951YSVZ

• Resolution (bits): 14 b
• Master Fclk: 400MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Data Rate: 25Mbps
• Rf Ic Case Style: TQFP
• No. Of Pins: 48
• Supply Voltage Range: 1.8V To 3.3V
• Operating Temperature Range: -40°C To +105°C
• Msl: MSL 3 - 168 Hours
• Ic Function: Direct Digital Synthesizer
• Digital Ic Case Style: TQFP
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Termination Type: SMD
• Ic Generic Number: 9951
• Base Number: 9951
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9951/PCB - BOARD EVAL FOR AD9951
• Lead Free Status / Rohs Status: Compliant

AD9951
INSTRUCTION BYTE
The instruction byte contains the following information:
Table 7.
MSB
R/Wb
R/Wb—Bit 7 of the instruction byte determines whether a read
or write data transfer will occur after the instruction byte write.
Logic High indicates read operation. Logic 0 indicates a write
operation.
X, X—Bits 6 and 5 of the instruction byte are Don’t Care.
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data transfer
portion of the communications cycle.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9951 and to run the internal state
machines. SCLK maximum frequency is 25 MHz.
CSB—Chip Select Bar. CSB is active low input that allows more
than one device on the same serial communications line. The
SDO and SDIO pins will go to a high impedance state when this
input is high. If driven high during any communications cycle,
that cycle is suspended until CS is reactivated low. Chip select
can be tied low in systems that maintain control of SCLK.
SDIO — Serial Data I/O. Data is always written into the
AD9951 on this pin. However, this pin can be used as a
bidirectional data line. Bit 9 of Register Address 0x00 controls
the configuration of this pin. The default is Logic 0, which
configures the SDIO pin as bidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9951 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
IOSYNC—It synchronizes the I/O port state machines without
affecting the addressable register’s contents. An active high
input on the IOSYNC pin causes the current communication
cycle to abort. After IOSYNC returns low (Logic 0), another
communication cycle may begin, starting with the instruction
byte write.
MSB/LSB TRANSFERS
The AD9951 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the Control Register 0x00 <8> bit.
The default value of Control Register 0x00 <8> is low (MSB
first). When Control Register 0x00 <8> is set high, the AD9951
D6
X
D5
X
D4
A4
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D3
A3
serial port is in LSB first format. The instruction byte must be
written in the format indicated by Control Register 0x00 <8>. If
the AD9951 is in LSB first mode, the instruction byte must be
written from least significant bit to most significant bit.
For MSB first operation, the serial port controller will generate
the most significant byte (of the specified register) address first
followed by the next lesser significant byte addresses until the
I/O operation is complete. All data written to (read from) the
AD9951 must be (will be) in MSB first order. If the LSB mode is
active, the serial port controller will generate the least signifi-
cant byte address first followed by the next greater significant byte
addresses until the I/O operation is complete. All data written to
(read from) the AD9951 must be (will be) in LSB first order.
Example Operation
To write the amplitude scale factor register in MSB first format,
apply an instruction byte of 0x02 (serial address is 00010(b)).
From this instruction, the internal controller will generate an
internal byte address of 0x07 (see the register map) for the first
data byte written and an internal address of 0x08 for the next
byte written. Since the amplitude scale factor register is two
bytes wide, this ends the communication cycle.
To write the amplitude scale factor register in LSB first format,
apply an instruction byte of 0x40. From this instruction, the
internal controller will generate an internal byte address of
0x08 (see the register map) for the first data byte written and an
internal address of 0x07for the next byte written. Since the
amplitude scale factor register is two bytes wide, this ends the
communication cycle.
Power-Down Functions of the AD9951
The AD9951 supports an externally controlled or hardware
power-down feature as well as the more common software
programmable power-down bits found in previous ADI DDS
products.
The software control power-down allows the DAC, PLL, input
clock circuitry, and digital logic to be individually powered
down via unique control bits (CFR1<7:4>). With the exception
of CFR1<6>, these bits are not active when the externally
controlled power-down pin (PWRDWNCTL) is high. External
power-down control is supported on the AD9951 via the
PWRDWNCTL input pin. When the PWRDWNCTL input pin
is high, the AD9951 will enter a power-down mode based on
the CFR1<3> bit. When the PWRDWNCTL input pin is low,
the external power-down control is inactive.
D2
A2
D1
A1
LSB
A0