CYP15G0401RB-BGXC Cypress Semiconductor Corp, CYP15G0401RB-BGXC Datasheet - Page 13

• Manufacturer Part Number: CYP15G0401RB-BGXC
• Description: IC RECEIVER HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401RB-BGXC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 0/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.69 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4RX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02111 Rev. **
character. To reduce the impact on external circuits that make
use of a recovered clock, the clock period is not stretched by
more than two bit-periods in any one clock cycle. When
operated with a character-rate output clock (RXRATE = LOW),
the output of properly framed characters may be delayed by
up to nine character-clock cycles from the detection of the
selected
half-character-rate output clock (RXRATE = HIGH), the output
of properly framed characters may be delayed by up to
fourteen character-clock cycles from the detection of the
selected framing character.
When RFMODE = MID (open), the Cypress-mode Multi-Byte
Framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased framing characters in the data
stream. In this mode, the Framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock does not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode, the character boundaries are only
adjusted if the selected framing character is detected at least
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
When RFMODE = HIGH, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the Framer does
not adjust the character clock boundary, but instead aligns the
character to the already recovered character clock. In this
mode, the data stream must contain a minimum of four of the
selected framing characters, received as consecutive
characters, on identical 10-bit boundaries, before character
framing is adjusted.
Framing for all channels is enabled when RFEN = HIGH. If
RFEN = LOW, the Framer for each channel is disabled. When
the framers are disabled, no changes are made to the
recovered character boundaries on any channel, regardless of
the presence of framing characters in the data stream.
10B/8B Decoder Block
The Decoder logic block performs three primary functions:
10B/8B Decoder
The framed parallel output of each Deserializer Shifter is
passed to the 10B/8B Decoder where, if the Decoder is
enabled (DECMODE ≠ LOW), it is transformed from a 10-bit
transmission character back to the original Data and Special
Character codes. This block uses the 10B/8B Decoder
patterns in Table 14 and Table 15 of this data sheet. Valid data
characters are indicated by a 000b bit-combination on the
associated RXSTx[2:0] status bits, and Special Character
codes are indicated by a 001b bit-combination on these same
status outputs. Framing characters, invalid patterns, disparity
• decoding the received transmission characters back into
• comparing generated BIST patterns with received
• generation of ODD parity on the decoded characters.
Data and Special Character codes
characters to permit at-speed link and device testing
framing
character.
When
operated
PRELIMINARY
with
a
errors, and synchronization status are presented as alternate
combinations of these status bits.
The 10B/8B Decoder operates in two normal modes, and can
also be bypassed. The operating mode for the Decoder is
controlled by the DECMODE input.
When DECMODE = LOW, the Decoder is bypassed and raw
10-bit characters are passed to the Output Register. In this
mode the Receive Elasticity Buffers are bypassed, and
RXCKSEL must be MID. This clock mode generates separate
RXCLKx± outputs for each receive channel.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using Table 14 and Table 15.
Received Special Code characters are decoded using the
Cypress column of Table 15.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using Table 14 and Table 15. Received Special
Code characters are decoded using the Alternate column of
Table 15.
Receive BIST Operation
The Receiver interfaces contain internal pattern generators
that can be used to validate both device and link operation.
These generators are enabled by the associated BRE[x]
signals listed in Table 2 (when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated receive
channel becomes a pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet pseudo-
random sequence that can be matched to an identical LFSR
in the attached Transmitter(s), the CYP15G0401TB for
example. If the receive channels are configured for common
clock operation (RXCKSEL ≠ MID) each pass must be
preceded by a 16-character Word Sync Sequence. Please
note that BIST cannot be used in a common clock configu-
ration (RXCKSEL ≠ MID) when using the CYP15G0401TB
device as the BIST generator, as the 16-character Word Sync
Sequence will not be present in the BIST pattern. When
synchronized with the received data stream, the associated
Receiver checks each character in the Decoder with each
character generated by the LFSR and indicates compare
errors and BIST status at the RXSTx[2:0] bits of the Output
Register. See Table 10 for details.
When the BISTLE signal is HIGH, any BRE[x] input that is
LOW enables the BIST generator/checker in the associated
Receive channel. When BISTLE returns LOW, the values of
all BRE[x] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned HIGH. All captured signals in the BIST Enable Latch
are set HIGH (i.e., BIST is disabled) following a device reset
(TRSTZ is sampled LOW).
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0. This D0.0 character is sent only once per BIST loop. The
status of the BIST progress and any character mismatches is
presented on the RXSTx[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period
per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. These same status values
CYP15G0401RB
Page 13 of 35
[+] Feedback