CYP15G0401RB-BGXC Cypress Semiconductor Corp, CYP15G0401RB-BGXC Datasheet - Page 2
![IC RECEIVER HOTLINK 256LBGA](/photos/28/19/281926/256-lbga_sml.jpg)
CYP15G0401RB-BGXC
Manufacturer Part Number
CYP15G0401RB-BGXC
Description
IC RECEIVER HOTLINK 256LBGA
Manufacturer
Cypress Semiconductor Corp
Series
HOTlink II™r
Type
Transceiverr
Datasheet
1.CYP15G0401RB-BGXC.pdf
(35 pages)
Specifications of CYP15G0401RB-BGXC
Package / Case
256-LBGA Exposed Pad, 32-HLBGA
Number Of Drivers/receivers
0/4
Protocol
Multiprotocol
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Product
PHY
Data Rate
1500 MBd
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current
0.69 A
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
4RX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYP15G0401RB-BGXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-02111 Rev. **
As
CYP15G0401RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, command, and BIST) with other
HOTLink devices. The receivers (RX) of the CYP15G0401RB
Quad HOTLink II consist of four byte-wide channels. Each
channel accepts a serial bit-stream from one of two
PECL-compatible differential line receivers and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. Each
recovered serial stream is deserialized and framed into
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system. The integrated 8B/10B Decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
a
second-generation
HOTLink
device,
PRELIMINARY
the
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. The receive interface may be configured to
present data relative to a recovered clock or to a local training
clock.
Each receive channel contains an independent BIST pattern
checker. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each receive section, and
across the interconnecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point
interconnecting backplanes on switches, routers, servers and
video transmission systems.
serial
links.
Some
CYP15G0401RB
applications
Page 2 of 35
include
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