CYP15G0401RB-BGXC Cypress Semiconductor Corp, CYP15G0401RB-BGXC Datasheet - Page 14

• Manufacturer Part Number: CYP15G0401RB-BGXC
• Description: IC RECEIVER HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401RB-BGXC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 0/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.69 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4RX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02111 Rev. **
are presented when the Decoder is bypassed and BIST is
enabled on a receive channel.
The status reported on RXSTx[2:0] by the BIST state machine
are listed in Table 10. When Receive BIST is enabled, the
same status is reported on the receive status outputs
regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In
Self-Test.” The sequence compared by the CYP15G0401RB
when RXCKSEL = MID is identical to that in the CY7B933 and
CY7C924DX, allowing interoperable systems to be built when
used at compatible serial signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by sixteen, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
When the receive paths are configured for common clock
operation (RXCKSEL ≠ MID), each pass must be preceded by
a 16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations (see
CYP15G0401TB datasheet for details on how to send a
16-character Word Sync Sequence from the remote trans-
mitter).
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low Latency
Framer is enabled (RFMODE = LOW), the Framer will
misalign to an aliased framing character within the BIST
sequence. If the Alternate Multi-Byte Framer is enabled
(RFMODE = HIGH) and the Receiver outputs are clocked
relative to a recovered clock, it is necessary to frame the
Receiver before BIST is enabled.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using an Elasticity Buffer read-clock that
is asynchronous in both frequency and phase from the
Elasticity Buffer write clock, or to use a read clock that is
frequency coherent but with uncontrolled phase relative to the
Elasticity Buffer write clock.
Each Elasticity Buffer is 10-characters deep, and supports a
twelve-bit wide data path. It is capable of supporting a decoded
character, three status bits, and a parity bit for each character
present in the buffer. The write clock for these buffers is always
the recovered clock for the associated read channel.
The read clock for the Elasticity Buffers may come from one of
three selectable sources. It may be a
The Elasticity Buffers are bypassed whenever the Decoders
are bypassed (DECMODE = LOW). When the Decoders and
Elasticity Buffers are bypassed, RXCKSELx must be set to
MID.
Receive Normal Data Operation
When RXCKSEL = LOW, all four receive channels are clocked
by TRGCLK. RXCLKB± and RXCLKD± outputs are disabled
• character-rate TRGCLK (RXCKSEL = LOW and
• recovered clock from an alternate receive channel
DECMODE ≠ LOW)
(RXCKSEL = HIGH and DECMODE ≠ LOW).
PRELIMINARY
(High-Z), and the RXCLKA± and RXCLKC± outputs present a
buffered and delayed form of TRGCLK. In this mode, the
Receive Elasticity Buffers are enabled. For TRGCLK clocking,
the Elasticity Buffers must be able to insert K28.5 characters
and delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
on these insertions and deletions is controlled in part by the
how the attached remote transmitter sends its data. Insertion
of a K28.5 character can only occur when the receiver has a
framing character in the Elasticity Buffer. Likewise, to delete a
framing character, one must also be present in the Elasticity
Buffer. To prevent a receive buffer overflow or underflow on a
receive channel, a minimum density of framing characters
must be present in the received data streams.
When RXCKSEL = MID (or open), each received channel
Output Register is clocked by the recovered clock for that
channel. Since no characters may be added or deleted, the
receiver Elasticity Buffer is bypassed.
When RXCKSEL = HIGH in independent channel mode, all
channels are clocked by the selected recovered clock. This
selection is made using the RXCLKB+ and RXCLKD+ signals
as inputs per Table 5. This selected clock is always output on
RXCLKA± and RXCLKC±. In this mode the Receive Elasticity
Buffers are enabled. When data is output using a recovered
clock (RXCKSEL = HIGH), the receive channels are not
allowed to insert and delete characters, except as necessary
for Elasticity Buffer alignment.
When the Elasticity Buffer is used, prior to reception of valid
data, a Word Sync Sequence (or at least four framing
characters) must be received to center the Elasticity Buffers.
The Elasticity Buffer may also be centered by a device reset
operation initiated by TRSTZ input. However, following such
an event, the CYP15G0401RB also requires a framing event
before it will correctly decode characters. When RXCKSEL =
HIGH, since the Elasticity Buffer is not allowed to insert or
delete framing characters, the transmit clocks on all received
channels must all be from a common source.
Table 5. Independent Recovered Clock Select
Power Control
The CYP15G0401RB supports user control of the powered up
or down state of each receive channel. The receive channels
are controlled by the RXLE signal and the values present on
the BRE[3:0] bus. Powering down unused channels will save
power and reduce system heat generation. Controlling system
power dissipation will improve the system performance.
Receive Channels
When RXLE is HIGH, the signals on the BRE[3:0] inputs
directly control the power enables for the receive PLLs and
analog circuits. When a BRE[3:0] input is HIGH, the
associated receive channel [A through D] PLL and analog
logic are active. When a BRE[3:0] input is LOW, the
RXCLKB+
0
0
1
1
RXCLKD+
0
1
0
1
RXCLKA±/RXCLKC± Clock
CYP15G0401RB
RXCLKA
RXCLKB
RXCLKC
RXCLKD
Source
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