PIC24FJ32GA002-I/SP Microchip Technology Inc., PIC24FJ32GA002-I/SP Datasheet - Page 175

• Manufacturer Part Number: PIC24FJ32GA002-I/SP
• Description: MCU, 16-Bit, 28-Pin, 32KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ32GA002-I/SP

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 32 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.1.3
REGISTER 18-1:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1:
RTCEN
R/W-0
R/W-0
CAL7
2:
3:
(2)
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
RTCC CONTROL REGISTERS
RTCEN: RTCC Enable bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
HALFSEC: Half-Second Status bit
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC output enabled
0 = RTCC output disabled
RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers;
the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL<7:0>:
00 = SECONDS
01 = HOURS
10 = DAY
11 =YEAR
R/W-0
CAL6
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
U-0
—
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
W = Writable bit
‘1’ = Bit is set
RTCWREN
R/W-0
R/W-0
CAL5
(2)
RTCSYNC
R/W-0
CAL4
PIC24FJ64GA004 FAMILY
R-0
Preliminary
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HALFSEC
R/W-0
CAL3
R-0
(3)
RTCOE
R/W-0
R/W-0
CAL2
x = Bit is unknown
RTCPTR1
R/W-0
R/W-0
CAL1
(1)
DS39881B-page 173
RTCPTR0
R/W-0
R/W-0
CAL0
bit 8
bit 0