PIC18F2520-I/SP Microchip Technology Inc., PIC18F2520-I/SP Datasheet - Page 265
PIC18F2520-I/SP
Manufacturer Part Number
PIC18F2520-I/SP
Description
28 Pin, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-ISP.pdf
(390 pages)
Specifications of PIC18F2520-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2520-I/SP
Manufacturer:
XLSEMI
Quantity:
35 000
Part Number:
PIC18F2520-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
TABLE 23-3:
2004 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
2:
File Name
Program Verification and
Code Protection
®
devices.
Unimplemented in PIC18F2420/4420 devices; maintain this bit set.
Unimplemented in PIC18F2425/4425 devices; maintain this bit set.
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
(PIC18F2420/4420)
Unimplemented
SUMMARY OF CODE PROTECTION REGISTERS
16 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
CODE-PROTECTED PROGRAM MEMORY FOR
PIC18F2420/2520/4420/4520
MEMORY SIZE/DEVICE
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
(PIC18F2520/4520)
WRTB
Bit 6
CPB
Unimplemented
—
—
—
Boot Block
32 Kbytes
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
PIC18F2420/2520/4420/4520
WRTC
Bit 5
Preliminary
—
—
—
—
—
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
1FFFFFh
Address
Range
Bit 4
—
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code pro-
tection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
EBTR3
WRT3
(Unimplemented Memory Space)
CP3
Bit 3
—
—
—
Block Code Protection
(1,2)
CPB, WRTB, EBTRB
(1,2)
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
(1,2)
Controlled By:
EBTR2
WRT2
CP2
Bit 2
—
—
—
(1)
(1)
(1)
EBTR1
WRT1
Bit 1
CP1
DS39631A-page 263
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—
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