PIC18F2520-I/SP Microchip Technology Inc., PIC18F2520-I/SP Datasheet - Page 361
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PIC18F2520-I/SP
Manufacturer Part Number
PIC18F2520-I/SP
Description
28 Pin, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-ISP.pdf
(390 pages)
Specifications of PIC18F2520-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2520-I/SP
Manufacturer:
XLSEMI
Quantity:
35 000
Part Number:
PIC18F2520-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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FIGURE 26-22:
TABLE 26-25: A/D CONVERSION REQUIREMENTS
2004 Microchip Technology Inc.
130
131
132
135
TBD
Legend: TBD = To Be Determined
Note 1:
Param
No.
Note 1:
2:
3:
4:
A/D DATA
SAMPLE
A/D CLK
T
T
T
T
T
ADRES
Symbol
AD
CNV
ACQ
SWC
BSF ADCON0, GO
DIS
ADIF
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
GO
2:
Q4
If the A/D clock source is selected as RC, a time of T
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert
Discharge Time
132
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
9
to V
SS
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
8
or V
PIC18F2420/2520/4420/4520
OLD_DATA
SS
7
Preliminary
Sample
to V
. . .
SAMPLING STOPPED
DD
CY
). The source impedance (R
CY
is added before the A/D clock starts.
cycle.
. . .
131
130
TBD
TBD
TBD
Min
0.7
1.4
1.4
0.2
11
—
2
(Note 4)
25.0
25.0
Max
12
—
—
—
1
3
(1)
(1)
1
Units
T
AD
s
s
s
s
s
s
s
S
) on the input channels is 50 .
0
T
V
T
A/D RC mode
V
-40 C to +85 C
0 C
OSC
OSC
DD
DD
AD
= 2.0V;
= 2.0V; A/D RC mode
based, V
based, V
clock divider.
to
NEW_DATA
DONE
Conditions
DS39631A-page 359
+85 C
T
CY
REF
REF
full range
3.0V
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