PIC18F2520-I/SP Microchip Technology Inc., PIC18F2520-I/SP Datasheet - Page 312
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PIC18F2520-I/SP
Manufacturer Part Number
PIC18F2520-I/SP
Description
28 Pin, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-ISP.pdf
(390 pages)
Specifications of PIC18F2520-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2520-I/SP
Manufacturer:
XLSEMI
Quantity:
35 000
Part Number:
PIC18F2520-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F2420/2520/4420/4520
24.2.2
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39631A-page 310
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
EXTENDED INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
=
=
ADDFSR 2, 23h
literal ‘k’
0
f
FSR(f) + k
None
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
1
1
Add Literal to FSR
ADDFSR f, k
Read
1110
Q2
03FFh
0422h
[ 0, 1, 2 ]
k
63
1000
Process
FSR(f)
Data
Q3
ffkk
Write to
FSR
kkkk
Q4
Preliminary
ADDULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
FSR2
PC
FSR2
PC
Q1
No
=
=
=
=
Operation
ADDULNK 23h
literal ‘k’
Add Literal to FSR2 and Return
ADDULNK k
0
FSR2 + k
(TOS)
None
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
1
2
Read
1110
Q2
No
03FFh
0100h
0422h
(TOS)
k
2004 Microchip Technology Inc.
63
PC
1000
Operation
FSR2,
Process
Data
Q3
No
11kk
Operation
Write to
FSR
kkkk
Q4
No
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