PIC16F690-E/P Microchip Technology Inc., PIC16F690-E/P Datasheet - Page 185

• Manufacturer Part Number: PIC16F690-E/P
• Description: 20 PIN, 7 KB FLASH, 256 RAM, 18 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F690-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 7 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 18
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the SSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
13.9
A Reset disables the SSP module and terminates the
current transfer.
TABLE 13-2:
© 2006 Microchip Technology Inc.
0Bh/8Bh/
10Bh/18Bh
0Ch
13h
14h
86h/186h
87h/187h
8Ch
94h
Legend:
Address
Note 1:
Sleep Operation
Effects of a Reset
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
INTCON
PIR1
SSPBUF
SSPCON
TRISB
TRISC
PIE1
SSPSTAT
PIC16F687/PIC16F689/PIC16F690 only.
Name
REGISTERS ASSOCIATED WITH SPI OPERATION
Synchronous Serial Port Receive Buffer/Transmit Register
TRISB7 TRISB6 TRISB5 TRISB4
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
WCOL
Bit 7
SMP
GIE
—
—
SSPOV
ADIE
Bit 6
PEIE
ADIF
CKE
PIC16F631/677/685/687/689/690
SSPEN
RCIE
RCIF
Bit 5
T0IE
D/A
Preliminary
INTE
TXIE
Bit 4
TXIF
CKP
P
SSPM3
RABIE
SSPIF
SSPIE
Bit 3
—
S
13.10 Bus Mode Compatibility
Table 13-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 13-1:
There is also a SMP bit which controls when the data is
sampled.
Standard SPI Mode
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
SSPM2
Terminology
Bit 2
T0IF
R/W
—
0, 0
0, 1
1, 0
1, 1
(1)
SSPM1
Bit 1
INTF
UA
—
SPI BUS MODES
SSPM0
RABIF
Bit 0
BF
—
CKP
Control Bits State
0
0
1
1
0000 0000
0000 0000
0000 000x
-000 0000
-000 0000
xxxx xxxx
1111 1111
Value on
1111 ----
POR,
BOR
DS41262C-page 183
uuuu uuuu
0000 0000
0000 0000
0000 000x
-000 0000
-000 0000
CKE
1111 1111
Value on
all other
1111 ----
Resets
1
0
1
0