PIC16F690-E/P Microchip Technology Inc., PIC16F690-E/P Datasheet - Page 43

• Manufacturer Part Number: PIC16F690-E/P
• Description: 20 PIN, 7 KB FLASH, 256 RAM, 18 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F690-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 7 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 18
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.2.2.6
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
REGISTER 2-6:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
2:
3:
4:
5:
PIC16F685/PIC16F690 only.
PIC16F685/PIC16F689/PIC16F690 only.
PIC16F687/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
PIR1 Register
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
Compare mode:
PWM mode:
Unused in this mode
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
ADIF
R/W-0
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
(5)
W = Writable bit
‘1’ = Bit is set
RCIF
PIC16F631/677/685/687/689/690
R-0
(3)
TXIF
(2)
R-0
Preliminary
(3)
(5)
(1)
(3)
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPIF
R/W-0
Note:
(4)
(4)
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
CCP1IF
R/W-0
software
(2)
x = Bit is unknown
TMR2IF
R/W-0
should
(1)
DS41262C-page 41
ensure
TMR1IF
R/W-0
bit 0
the