ST7540TR STMicroelectronics, ST7540TR Datasheet - Page 23

IC TXRX FSK POWER LINE 28-TSSOP

ST7540TR

Manufacturer Part Number
ST7540TR
Description
IC TXRX FSK POWER LINE 28-TSSOP
Manufacturer
STMicroelectronics
Type
Transceiverr
Datasheet

Specifications of ST7540TR

Number Of Drivers/receivers
1/1
Voltage - Supply
5 V ~ 9 V
Mounting Type
Surface Mount
Package / Case
28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
For Use With
497-5485 - BOARD EVAL ST7540 PWR LINE TXRX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Protocol
-
Lead Free Status / Rohs Status
Compliant
Other names
497-5528-2

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ST7540
6.6
Figure 11. Data transmission
Figure 12. Data transmission
Receiving mode
The receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RX_IN Pin using SV
by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting
one bit in the Control Register. The Input Stage features a wide dynamic range to receive
Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is
automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a
Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz
max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated
by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter)
improves the Signal to Noise ration before sending the signal to the FSK demodulator. The
FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital
filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced to “0” or “1” (according the UART/SPI pin level) when neither mark
or space frequencies are detected on RX_IN Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have
a correct demodulation.
While ST7540 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line
Interface included, is turned off. This allows the device to achieve a very low current
consumption (5mA typ).
REG_DATA
REG_DATA
CLR_T
CLR_T
RxTx
RxTx
TxD
RxD
RxD
TxD
T
T
S
S
T
T
H
H
T
T
B
B
T
T
CR
CR
T
CR
T
T
CC
CC
control register read
control register write
BIT23
BIT23
T
S
T
H
T
DS
SS
BIT22
BIT22
T
as ground reference and then pre-filtered
DH
data reception timing diagram
data reception timing diagram
T
CR
T
T
Functional description
CR
CR
T
T
CC
CC
T
T
DS
DS
T
T
DH
DH
D03IN1405
D03IN1401
23/44

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