ST7540TR STMicroelectronics, ST7540TR Datasheet - Page 24

• Manufacturer Part Number: ST7540TR
• Description: IC TXRX FSK POWER LINE 28-TSSOP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of ST7540TR

• Number Of Drivers/receivers: 1/1
• Voltage - Supply: 5 V ~ 9 V
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• For Use With: 497-5485 - BOARD EVAL ST7540 PWR LINE TXRX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Protocol: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 497-5528-2

Functional description
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Figure 13. ST7540 PLL lock-in range
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Receiving Sensitivity Level Selection
It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see
Table
the control register setting the sensitivity equal to BU threshold). Increasing the device
sensitivity allows to improve the communication reliability when the ST7540 sensitivity
is the limiting factor.
Synchronization Recovery System (PLL)
ST7540 embeds a Clock Recovery System to feature a Synchronous data exchange
with the Host Controller. The clock recovery system is realized by means of a second
order PLL. In Synchronous mode, data on the data line (RxD) are stable on CLR/T line
rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN
Range). The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock
condition RxD line is forced to “0” or “1” according to the UART/SPI pin level and CLR/T
is forced to “0” only if the Detection Method “Preamble Detection With Conditioning” is
selected.When PLL is in unlock condition it is sensitive to RxD Rising and Falling
Edges. The maximum number of transition required to reach the lock-in condition is 5.
When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the
CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal
symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only
to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL
into the un-lock condition.
Carrier/Preamble Detection
The Carrier/Preamble Block is a digital Frequency detector Circuit.
It can be used to manage the MAINS access and to detect an incoming signal.
Two are the possible setting:
–
–
Carrier Detection
Preamble Detection
12) or setting to ‘1’ the TxD pin during reception phase (this condition overcomes
CLR/T
RxD
LOCK-IN RANGE
D03IN1417
ST7540