IDT82V2048EBBG IDT, Integrated Device Technology Inc, IDT82V2048EBBG Datasheet - Page 32

• Manufacturer Part Number: IDT82V2048EBBG
• Description: IC LINE INTERFACE UNIT 208-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2048EBBG

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 208-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1704; 82V2048EBBG

OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.10 MCLK AND TCLK
3.10.1 MASTER CLOCK (MCLK)
MHz or 37.056 MHz for T1/J1 applications and 2.048 MHz or 49.152 MHz
in E1 mode. This reference clock is used to generate several internal ref-
erence signals:
•
•
•
•
•
MCLK and TCLKn. The missing of MCLK will set all the eight TTIP/TRING
to high impedance state.
MCLK is an independent, free-running reference clock. MCLK is 1.544
Figure-20
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during a blue alarm Transmit All Ones (TAOS), all
zeros, PRBS/QRSS and inband loopback patterns if it is selected
as the reference clock. For ATAO and AIS, MCLK is always used as
the reference clock.
normal operation mode
shows the chip operation status in different conditions of
clocked
TCLKn status?
Figure-20 TCLK Operation Flowchart
generates transmit clock loss
transmitter n enters high
interrupt if not masked
impedance status and
32
L/H
3.10.2 TRANSMIT CLOCK (TCLK)
The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0,
02H...). During Transmit All Ones, PRBS/QRSS patterns or Inband Loop-
back Code, either TCLKn or MCLK can be used as the reference clock. This
is selected by the PATT_CLK bit (MAINT0, 0AH...).
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0AH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0AH) is set to ‘1’.
bit (STAT0, 14H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
is not using MCLK to transmit internal patterns (TAOS, All Zeros, PRBS and
in-band loopback code). When TCLKn is detected again, TCLK_LOS bit
(STAT0, 14H...) will be cleared. The reference frequency to detect a TCLKn
loss is derived from MCLK.
clocked
The TCLKn is used to sample the transmit data on TDn/TDPn, TDNn.
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
all transmitters high
impedance status
MCLK=H/L?
TEMPERATURE RANGES
yes
INDUSTRIAL