IDT82V2048EBBG IDT, Integrated Device Technology Inc, IDT82V2048EBBG Datasheet - Page 7

IC LINE INTERFACE UNIT 208-PBGA

IDT82V2048EBBG

Manufacturer Part Number
IDT82V2048EBBG
Description
IC LINE INTERFACE UNIT 208-PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
Line Interface Units (LIUs)r
Datasheet

Specifications of IDT82V2048EBBG

Protocol
E1
Voltage - Supply
3.13 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
208-PBGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
800-1704
82V2048EBBG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT82V2048EBBG
Manufacturer:
IDT
Quantity:
5
Part Number:
IDT82V2048EBBG
Manufacturer:
IDT Integrated Device Technolo
Quantity:
135
Part Number:
IDT82V2048EBBG
Manufacturer:
NSC
Quantity:
60
Part Number:
IDT82V2048EBBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
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LIST OF FIGURES
Block Diagram ................................................................................................................. 2
IDT82V2048E PQFP208 Package Pin Assignment ........................................................ 8
IDT82V2048E PBGA208 Package Pin Assignment (top view) ....................................... 9
E1 Waveform Template Diagram .................................................................................. 16
E1 Pulse Template Test Circuit ..................................................................................... 16
DSX-1 Waveform Template .......................................................................................... 16
T1 Pulse Template Test Circuit ..................................................................................... 17
Receive Path Function Block Diagram .......................................................................... 21
Transmit/Receive Line Circuit ....................................................................................... 21
Monitoring Receive Line in Another Chip ...................................................................... 22
Monitor Transmit Line in Another Chip .......................................................................... 22
G.772 Monitoring Diagram ............................................................................................ 23
Jitter Attenuator ............................................................................................................. 24
LOS Declare and Clear ................................................................................................. 25
Analog Loopback .......................................................................................................... 28
Digital Loopback ............................................................................................................ 28
Remote Loopback ......................................................................................................... 28
Auto Report Mode ......................................................................................................... 30
Manual Report Mode ..................................................................................................... 31
TCLK Operation Flowchart ............................................................................................ 32
Serial Processor Interface Function Timing .................................................................. 33
JTAG Architecture ......................................................................................................... 55
JTAG State Diagram ..................................................................................................... 58
Transmit System Interface Timing ................................................................................ 66
Receive System Interface Timing ................................................................................. 66
E1 Jitter Tolerance Performance .................................................................................. 67
T1/J1 Jitter Tolerance Performance .............................................................................. 67
E1 Jitter Transfer Performance ..................................................................................... 69
T1/J1 Jitter Transfer Performance ................................................................................ 69
JTAG Interface Timing .................................................................................................. 70
Serial Interface Write Timing ......................................................................................... 71
Serial Interface Read Timing with SCLKE=1 ................................................................ 71
Serial Interface Read Timing with SCLKE=0 ................................................................ 71
Non_multiplexed Motorola Read Timing ....................................................................... 72
Non_multiplexed Motorola Write Timing ....................................................................... 73
Non_multiplexed Intel Read Timing .............................................................................. 74
Non_multiplexed Intel Write Timing .............................................................................. 75
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TEMPERATURE RANGES
INDUSTRIAL

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