DS80C320-MCG+ Dallas Semiconductor, DS80C320-MCG+ Datasheet - Page 28

• Manufacturer Part Number: DS80C320-MCG+
• Description: Microcontroller, 8051 Comp., 4 8-Bit I/O Ports, 64K ROM/RAM, 25 MHz, 5 V, PDIP40
• Manufacturer: Dallas Semiconductor

Specifications of DS80C320-MCG+

• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: UART
• Memory Type: ROMless
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 0 Bytes
• Ram Size: 256 Bytes
• Speed: 25 MHz
• Timers: 3-16-bit
• Voltage, Range: 4.25-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MOVX CHARACTERISTICS—DS80C323
Note: t
t
MCS
Data Hold After Read
Data Float After Read
ALE Low to Valid Data In
Port 0 Address to Valid Data
In
Port 2 Address to Valid Data
In
ALE Low to
Low
Port 0 Address Valid to
or
Port 2 Address Valid to
or
Data Valid to
Data Hold After Write
ALE High
RD
RD
RD
RD
WR
WR
WR
for each Stretch selection.
Pulse Width
Low to Valid Data In
Low to Address Float
or
Pulse Width
MCS
PARAMETER
WR
Low
Low
is a time period related to the Stretch memory cycle selection. The following table shows the value of
High to
RD
WR
or
Transition
WR
M2
0
0
0
0
1
1
1
1
RD
RD
M1
SYMBOL
0
0
1
1
0
0
1
1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVWL1
AVWL2
t
AVDV1
AVDV2
WLWH
QVWX
WHQX
WHLH
RLDV
RHDX
RHDZ
LLWL
RLRH
LLDV
RLAZ
M0
0
1
0
1
0
1
0
1
0.5t
1.5t
1.5t
2.5t
3 machine cycles (default)
2t
2t
2t
2t
28 of 40
t
t
t
t
t
CLCL
CLCL
CLCL
t
MCS
MCS
CLCL
CLCL
CLCL
CLCL
CLCL
MIN
CLCL
CLCL
CLCL
CLCL
VARIABLE CLOCK
-14
MOVX CYCLES
-1
0
2 machine cycles
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
-11
-11
-10
-13
-15
-11
-11
-10
-13
-5
-18
-11
-27
-25
1.5t
2.5t
2t
2.5t
3.5t
CLCL
0.5t
1.5t
2t
3t
CLCL
CLCL
t
(Note 5)
2t
t
CLCL
t
MAX
MCS
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
-42+t
CLCL
CLCL
14
-45+t
-59+t
-36
+16
-32
-5
-40
-7
-43
-58
+7
+8
MCS
MCS
MCS
12 t
16 t
20 t
24 t
28 t
4 t
8 t
t
MCS
0
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0