DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet
DS80C320-ECD
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DS80C320-ECD Summary of contents
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SECTION 1: INTRODUCTION The Dallas Semiconductor High-Speed Microcontroller is an 8051-compatible device that provides improved performance and power consumption compared to the original version. It retains instruction set and object code compatibility with the 8051, yet performs the ...
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... SECTION 2: ORDERING INFORMATION The High-Speed Microcontroller family follows the part numbering convention shown below. Note that all combinations of devices are not currently available. Please refer to individual data sheets for the available versions. DS80C320-MCG OPERATING VOLTAGE: SPEED MHz G 25 MHz L 33 MHz ...
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SECTION 3: ARCHITECTURE The High-Speed Microcontroller is based on the industry standard 80C52. The core is an accumulator based architecture using internal registers for data storage and peripheral control. It executes the standard 8051 instruction set. This section provides a ...
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In general, during a read operation, software reads the state of the external pin. Each port is represented by a SFR location. Timer/Counters Three 16-bit Timer/Counters are available in the High-Speed Microcontroller. Each timer ...
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POWER MONITOR Some members of the High-Speed Microcontroller family incorporate a band-gap reference and analog circuitry to monitor the power supply conditions. V will issue an optional early warning Power-fail interrupt. If power continues to fall, the Power Monitor will ...
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... Power-fail Interrupt Data Pointers Data Pointer Decrement Power Management Modes Ring Oscillator EMI Reduction Mode Real-Time Clock Nonvolatile SRAM Pulse Width Modulation A/D Converter Operating Voltage Table 3-1 DS80C310 DS80C320 DS80C323 DS83C520 Mask ROM 256 bytes 256 bytes 256 bytes 256 bytes ...
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SECTION 4: PROGRAMMING MODEL This section provides a programmer’s overview of the High-Speed Microcontroller core. It includes information on the memory map, on-chip RAM, Special Function Registers (SFRs), and instruction set. The programming model of the High-Speed Microcontroller is very ...
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SFRs are accessed directly between 80h and FFh (128 to 255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations. Scratchpad RAM is available for general purpose data storage commonly ...
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REGISTER MAP Figure 4-2 FFh 7Fh 0000h SCRATCHPAD REGISTER ADDRESSING Figure 4-3 FFh 7Fh 2Fh 7F 2Eh 77 2Dh 6F 2Ch 67 2Bh 5F 2Ah 57 29h 4F 28h 47 27h 3F 26h 37 25h 2F 24h 27 23h 1F ...
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SPECIAL FUNCTION REGISTERS The High-Speed Microcontroller, like the 8051, uses Special Function Registers (SFRs) to control peripherals and modes. In many cases, an SFR will control individual functions or report status on individual functions. The SFRs reside in register locations ...
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S80C310 SPECIAL FUNCTION REGISTER RESET VALUES Tables 4-2 REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 TMOD 0 0 ...
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... DS80C320/DS80C323 SPECIAL FUNCTION REGISTER LOCATIONS Table 4-3 REGISTER BIT 7 BIT 6 SP DPL DPH DPL1 DPH1 DPS 0 0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/ T TL0 TL1 TH0 TH1 CKCON WD1 WD0 P1 P1.7 P1.6 EXIF IE5 IE4 SCON0 SM0/FE_0 SM1_0 SBUF0 P2 P2.7 P2 ES1 ...
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... DS80C320/DS80C323 SPECIAL FUNCTION REGISTER RESET VALUES Table 4-4 REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 TMOD 0 0 TL0 0 0 TL1 0 0 TH0 0 0 TH1 0 0 CKCON EXIF 0 0 SCON0 ...
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DS83C520/DS87C520 SPECIAL FUNCTION REGISTER LOCATIONS Table 4-5 REGISTER BIT 7 BIT 6 P0 P0.7 P0.6 SP DPL DPH DPL1 DPH1 DPS 0 0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/ T TL0 TL1 TH0 TH1 CKCON WD1 WD0 ...
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DS83C520/DS87C520 SPECIAL FUNCTION REGISTER RESET VALUES Table 4-6 REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 ...
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DS87C530 SPECIAL FUNCTION REGISTER LOCATION Tables 4-7 REGISTER BIT 7 BIT 6 P0 P0.7 P0.6 SP DPL DPH DPL1 DPH1 DPS 0 0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/ T TL0 TL1 TH0 TH1 CKCON WD1 WD0 ...
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DS87C530 SPECIAL FUNCTION REGISTER LOCATION Tables 4-7( Cont.) REGISTER BIT 7 BIT 6 EIP - - RTCC SSCE SCE RTCSS RTCS 0 0 RTCM 0 0 RTCH RTCD0 RTCD1 Shaded bits are Timed Access protected BIT 5 BIT 4 BIT ...
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DS87C530 SPECIAL FUNCTION REGISTER RESET VALUES Tables 4-8 REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 ...
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RTCD1 SPECIAL SPECIAL SPECIAL FUNCTION REGISTERS Most of the unique features of the High-Speed Microcontroller family are controlled by bits in special function registers (SFRs) located in unused locations in the 8051 SFR map. This allows for increased functionality while ...
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Data Pointer High 0 (DPH SFR 83h DPH.7 DPH.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Data Pointer High 0. This register is the high byte of the standard 80C32 16-bit DPH.7-0 data pointer. DPL and ...
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Power Control (PCON SFR 87h SMOD_0 SMOD0 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset SMOD_0 Serial Port 0 Baud Rate Doubler Enable. This bit enables/disables the Bit 7 serial baud rate doubling function for Serial Port ...
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Timer/Counter Control (TCON SFR 88h TF1 TR1 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Timer 1 Overflow Flag. TF1 maximum count as defined by the current mode. This bit can be cleared by Bit 7 software ...
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Timer Mode Control (TMOD SFR 89h GATE C/ T RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset GATE Timer 1 Gate Control. This bit enable/disables the ability of Timer 1 to increment. Bit Timer ...
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Timer 0 LSB (TL0 SFR 8Ah TL0.7 TL0.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Timer 0 LSB. This register contains the least significant byte of Timer 0. TL0.7-0 Bits 7-0 Timer 1 LSB (TL1) 7 ...
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Clock Control (CKCON SFR 8Eh WD1 WD0 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer WD1, WD0 time-out period. The timer divides the crystal frequency by ...
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MD2, MD1, MD0 Stretch MOVX Select 2-0. These bits select the time by which external MOVX cycles are to be stretched. This allows slower memory or peripherals to be Bits 2-0 accessed without using ports or manual software intervention. The ...
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Port 1 (P1 SFR 90h P1.7 P1.6 INT4 INT5 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset General Purpose I/O Port 1. This register functions as a general purpose I/O P1.7-0 port. In addition, all the pins ...
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... This bit must be cleared before XTOFF can be set to 1. This bit is set to 1 after a power-on reset, and unchanged by all other forms of reset. This bit is not used on the DS80C310 or DS80C320 and will be 1 when read. ...
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Ring Oscillator Select. This bit selects the clock source following a resume RGSL from Stop mode. Using the ring oscillator to resume from Stop mode allows Bit 1 almost instantaneous start-up. This bit is cleared to 0 after a power-on ...
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RTC Trim Register (TRIM SFR 91h E4K X12/ 6 RT-* RT-* R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See description E4K External 4096 Hz RTC Signal Enable. This bit enables the output of a Bit 7 4096 Hz ...
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Serial Port 0 Control (SCON0) 7 SFR 98h SM0/FE_0 SM1_0 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Serial Port Mode These bits control the mode of serial port 0. In addition the SM0-2 SM0 and SM2_0 bits have ...
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... During external memory cycles, this port will contain the MSB of the address. The Port 2 latch does not control general purpose I/O pins on the DS80C310 and DS80C320, but is still used to hold the address MSB during register-indirect data memory operations such as MOVX A, @R1. ...
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Interrupt Enable (IE SFR A8h EA ES1 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Global Interrupt Enable. This bit controls the global masking of all interrupts EA except Power-Fail Interrupt, which is enabled by the EPFI ...
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High-Speed Microcontroller User’s Guide 34 of 175 ...
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Slave Address Register 0 (SADDR0 SFR A9h SADDR0.7 SADDR0.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Slave Address Register 0. This register is programmed with the given or SADDR0.7-0 broadcast address assigned to serial port 0. ...
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Port 3 (P3 SFR B0h P3.7 P3 RW-1 RW-1 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Purpose I/O Port 3. This register functions as a general purpose I/O port. In P3.7-0 addition, all the pins have ...
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Interrupt Priority (IP SFR B8h - PS1 - RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Bit 7 Reserved. Read data is indeterminate. PS1 Serial Port 1 Interrupt. This bit controls the priority of the serial port 1 ...
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Slave Address Mask Enable Register 0 (SADEN0 SFR B9h SADEN0.7 SADEN0.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Slave Address Mask Enable Register 0. This register functions as a mask SADEN0.7-0 when comparing serial port 0 ...
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Serial Port Control (SCON1) 7 SFR C0h SM0/FE_1 SM1_1 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Serial Port 1 Mode. These bits control the mode of serial port 1 as shown SM0-2 below. In addition, the SM0 and ...
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Receive Enable. REN_1 register. Bit Serial port 1 reception disabled Serial port 1 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0). th TB8_1 9 Transmission Bit State. This bit defines the state ...
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ROM Size Select (ROMSIZE SFR C2h - - R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Bits 7-3 These bits are reserved. Read data is indeterminate. ROM Size Select 2-0. This register is used to select the maximum on-chip ...
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Power Management Register (PMR SFR C4h CD1 CD0 RW-0 RW-1 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See description Clock Divide Control 1-0. These bits select the number of crystal oscillator CD1, CD0 clocks required to generate one ...
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ALE Disable. This bit disables the expression of the ALE signal on the device ALEOFF pin during all on-board program and data memory accesses. External memory Bit 2 accesses will automatically enable ALE independent of ALEOFF ALE expression ...
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Status Register (STATUS SFR C5 PIP HIP R-0 R-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See description Power Fail Priority Interrupt Status. When set, this bit indicates that software PIP is currently servicing a power-fail interrupt. It ...
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Time Access Register (TA SFR C7h TA.7 TA.6 W-1 W-1 W=Unrestricted Write, -n=Value after Reset Timed Access. Correctly accessing this register permits modification of timed TA.7-0 access protected bits. Write AAh to this register first, followed within 3 ...
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TCLK Transmit Clock Flag. This bit determines the serial port 0 timebase when Bit 4 transmitting data in serial modes Timer 1 overflow is used to determine transmitter baud rate for serial port 0. 1 ...
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Timer 2 Mode (T2MOD SFR C9h - - R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Bits 7-2 Reserved. Read data will be indeterminate. T2OE Timer 2 Output Enable. This bit enables/disables the clock output function of the T2 ...
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Timer 2 LSB (TL2 SFR CCh TL2.7 TL2.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Timer 2 LSB. This register contains the least significant byte of Timer 2. TL2.7-0 Bits 7-0 Timer 2 MSB (TH2) 7 ...
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Program Status Word (PSW SFR D0h CY AC RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset CY Carry Flag. This bit is set when if the last arithmetic operation resulted in a carry (during addition ...
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Watchdog Control (WDCON SFR D8h SMOD POR RW-0 RW-* R=Unrestricted Read, W=Unrestricted Write, T=Timed Access Write Only, SMOD Serial Modification. This bit controls the doubling of the serial port 1 baud rate Bit 7 in modes 1, 2, ...
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WDIF Watchdog Interrupt Flag. This bit, in conjunction with the Watchdog Timer Bit 3 Interrupt Enable bit, EWDI (EIE.4), and Enable Watchdog Timer Reset bit (WDCON.1), indicates if a watchdog timer event has occurred and what action will be taken. ...
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Accumulator (A or ACC SFR E0h ACC.7 ACC.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Accumulator. This register serves as the accumulator for arithmetic operations. ACC.7 functionally identical to the accumulator found in the ...
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B Register ( SFR F0h B.7 B.6 RW-0 RW-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset B.7-0 B Register. This register serves as a second accumulator for certain arithmetic operations functionally identical to the B register ...
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Real Time Alarm Minute Register (RTAM SFR F4h 0 0 R-0 R-0 R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset See Description Bits 7-6 Reserved. These bits will be 0 when read. RTAM.5-0 Real Time Alarm Minute. ...
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Extended Interrupt Priority (EIP SFR F8h - - R=Unrestricted Read, W=Unrestricted Write Value after Reset Bits 7-6 Reserved. These bits will be 0 when read. PRTCI Real Time Clock Interrupt Priority. This bit controls the priority ...
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Real Time Clock Control Register (RTCC SFR F9h SSCE SCE RW-* RW-* R=Unrestricted Read, W=Unrestricted Write, T=Timed Access Write Only, SSCE RTC Subsecond Register Compare Enable. This bit enables a match Bit 7 between the Real Time Alarm ...
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RTCRE RTC Read Enable. This bit temporarily halts internal updating of the RTC to allow software to read the current time. No loss of time will occur. This bit will Bit 3 be cleared to 0 following any reset. Attempts ...
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Real Time Clock Subsecond Register (RTCSS SFR FAh RTCSS.7 RTCSS.6 R*-* R*-* R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See Description RTCSS.7-0 Real Time Clock Subseconds. This register represents the subsecond value of the RTC. It can be ...
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Real Time Clock Hour Register (RTCH SFR FDh DOW2 DOW1 R*W*-* R*W*-* R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See Description DOW.2-0 Real Time Clock Day of the Week. These bits represent the current day of the week. ...
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Real Time Clock Day Register 1 (RTCD1 SFR FFh RTCD1.7 RTCD1.6 R*W*-* R*W*-* R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset Real Time Clock Day Register 1. This register contains the most significant RTCD1.7-0 byte of the 16-bit current ...
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INSTRUCTION TIMING All instructions in the High-Speed Microcontroller perform the same functions as their 80C32 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute ...
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Each mode of addressing is summarized below. Note that many instructions (such as ADD) have multiple addressing modes available. High-Speed Microcontroller User’s Guide 62 of 175 ...
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Register Addressing Register Addressing is used for operands that are located in one of the eight Working Registers (R7-R0). These are the currently selected Working Register bank, which reside in the lower 32 bytes of Scratchpad RAM. A register bank ...
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Register Indirect Addressing This mode is used to access the Scratchpad RAM locations above 7Fh. It can also be used to reach the lower RAM (0h - 7Fh) if needed. The address is supplied by the contents of the Working ...
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Register Indirect with Displacement Register Indirect Addressing with Displacement is used to access data in lookup tables in program memory space. The location is created using a base address with an index. The base address can be either the PC ...
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PROGRAM STATUS FLAGS All Program Status Flags are contained in the Program Status Word at SFR location D0h. It contains flags that reflect the status of the CPU and the result of selected operations. The flags are summarized below. The ...
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SECTION 5: CPU TIMING The timing of the High-Speed Microcontroller is the area with the greatest departure from the original 8051 series. This section will briefly explain the timing and also compare it to the original. OSCILLATOR The High-Speed Microcontroller ...
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CRYSTAL CONNECTION Figure 5 CLOCK SOURCE INPUT Figure 5-2 CLOCK OSCILLATOR INSTRUCTION TIMING The clock source, whether crystal or oscillator, supplies the internal functions with a precise time base. The clock is used to create the basic unit ...
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Due to the limited number of edges within a machine cycle, selected events must occur between edges. The High-Speed Microcontroller employs sophisticated circuits to create half and quarter clock events. That is, some events occur between clock edges. Such circuits ...
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Note that in the first example, the first memory access is the opcode. The second memory access is the location of the operand in the register map. Since the result is stored in an internal register, this operation does not ...
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TWO CYCLE INSTRUCTION TIMING Figure 5-4 Example: ANL A, direct: INSTRUCTION C2 C1 CLK ALE PSEN A7-0 AD0- PIC POR *Shaded areas are held in a weak latch on the port until overdriven. THREE CYCLE INSTRUCTIONS Three cycle instructions come ...
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FOUR CYCLE INSTRUCTIONS All four cycle instructions require more time than the associated number of bytes. These are all program branching instructions that can move program control to a new location. The four cycle instructions use either ...
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PSEN Example 3: INC DPTR PSEN *Shaded areas are held in a weak latch on the port until overdriven. FOUR CYCLE INSTRUCTION TIMING Figure 5–6 Example 1: CJNE A, #data, addr PSEN Example 2: RET A3h B4h d7–d0 a7–a0 22h ...
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PSEN FIVE CYCLE INSTRUCTION TIMING Figure 5–7 Example: MUL A,B PSEN *Shaded areas are held in a weak latch on the port until overdriven. COMPARISON TO THE 8051 The original 8051 had a 12 clock architecture. A machine cycle needed ...
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Table 5-2 provides a summary by instruction type. Note that many of the instructions provide multiple opcodes example, the ADD A, Rn instruction can act on one of 8 working registers. There are 8 opcodes for this instruction ...
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INSTRUCTION TIMING COMPARISON Table 5-1 High–Speed Microcontroller is abbreviated as HSM. HEX INSTRUCTION CODE ADD A, Rn 28..2F ADD A, direct 25 ADD A, @Ri 26..27 ADD A, #data 24 ADDC A, Rn 38..3F ADDC A, direct 35 ADDC A, ...
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RLC RRC A 13 SWAP A C4 MOV A, Rn E8..EF MOV A, direct E5 MOV A, @Ri E6..E7 MOV A, #data 74 MOV Rn, A F8..FF MOV Rn, direct A8..AF MOV Rn, #data 78..7F ...
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RETI 32 AJMP addr 11 Hex code Hex code=01, 21, 41, Byte 1 61, 81, A1, C1 LJMP addr 16 2 JMP @A+DPTR 73 SJMP rel 80 JZ rel 60 JNZ rel 70 JC rel 40 JNC rel ...
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INSTRUCTION SPEED SUMMARY Table 5-2 INSTRUCTION CATEGORY Total Instructions: One Cycle One Byte Total Instructions: Two Cycle One Byte Total Instructions: Two Cycle Two Bytes X1.5 Total Instructions: Two cycle Two Bytes X3.0 Total Instructions: Three Cycle One Byte Total ...
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... Products with no on-chip program memory such as the DS80C320 will always use the Expanded bus. These devices have no Port 0 latch since the port is dedicated for memory operations. Devices which incorporate on-chip MOVX data memory operate in a similar fashion, except that the enables when accessing an external SRAM ...
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Another advantage of internal data memory is that it guarantees a 2 machine cycle data memory access. This data can be made nonvolatile on the DS87C530 through the use of an external battery. Restricting memory operations within the on–chip memory ...
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... PROGRAM MEMORY INTERCONNECT The program memory interconnect scheme for the High-Speed Microcontroller family is shown in Figure 6-1. This example uses the DS80C320 and one 32K x 8 EPROM. The Program Store Enable (PSEN) signal is used to provide an output enable to the EPROM. It can also be used to provide a chip enable, but this produces less favorable timing ...
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... Expanded bus. The physical connection of off-chip data memory is shown in Figure 6-3. This illustrates a DS80C320 with interfaced with an 8K SRAM. The data memory map begins at address 0000h since the DS80C320 has no on-chip data memory. A similar interconnection scheme would be implemented if a device with internal data memory, such as the DS87C520 would be used ...
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... PROGRAM MEMORY SIGNALS Figure 6-2 PSEN PORT 0 PORT 2 XTAL1 DATA MEMORY INTERFACE Figure 6-3 ALE DS80C320 RD (P3.7) WR SINGLE CYCLE ALE LSB DATA ADDR MSB ADDRESS LBS ADDRESS 74F373 LATCH DATA BUS MSB ADDRESS (P3. 175 High-Speed Microcontroller User’s Guide ( SRAM ...
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... The example program listed below was original code written for an 8051 and requires a total of 1869 machine cycles on the DS80C320. This takes 299 s to execute at 25 MHz. The new code using the Dual DPTR requires only 1097 machine cycles taking 175.5 s. The Dual DPTR saves 772 machine cycles or 123 ...
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BYTE BLOCK MOVE WITH DUAL DATA POINTER ; SH and SL are high and low byte source address and DL are high and low byte of destination address. ; DPS is the data pointer select. Reset condition ...
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DATA MEMORY TIMING Data memory timing refers to the execution of the MOVX instruction. This instruction includes a program fetch memory access, then a read or write memory access. The program fetch for a MOVX instruction is no different from ...
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Note that the first Stretch value does not follow the pattern of adding four clocks to the strobe. This is because the first Stretch uses one clock to create additional set-up and one clock to create additional hold time. Systems ...
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THREE CYCLE MOVX INSTRUCTION Figure 6-5a Last Cycle of Previous Instruction CLK ALE PSEN WR A0-A7 D0-D7 AD0-AD7 MOVX Instruction Address MOVX Instruction PORT 2 A8-A15 THREE CYCLE DATA MEMORY WRITE (RESET DEFAULT) First Second Machine ...
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FOUR CYCLE MOVX INSTRUCTION Figure 6-5b Last Cycle of Previous Instruction CLK ALE PSEN WR A0-A7 D0-D7 AD0-AD7 MOVX Instruction Instruction Address Address MOVX Instruction PORT 2 A8-A15 First Second Third Machine Machine Machine ...
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SECTION 7: POWER MANAGEMENT The High-Speed Microcontroller has several features that relate to power consumption and management. They provide a combination of controlled operation in unreliable power applications and reduced power consumption in portable or battery powered applications. The range ...
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POWER-FAIL RESET Devices which incorporate the power-fail reset will automatically invoke a reset when This will halt device operation, and place all outputs in their reset state. This state will continue to RST be held until V ...
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POWER CYCLE OPERATION Figure 7 PFW V RST V SS INTERRUPT SERVICE ROUTINE XTAL1 INTERNAL RESET WATCHDOG WAKE UP The Watchdog Wake up is more of an application than a feature. It allows a system to enter ...
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WDCON.2 WTRF - Watchdog Timer Reset Flag. Hardware will set this bit when the Watchdog Timer causes a reset. Software can read it, but must clear it manually. A Power-fail Reset will also clear the bit. This bit assists software ...
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IDLE MODE Idle mode suspends all CPU processing by holding the program counter in a static state. No program values are fetched and no processing occurs. This saves considerable power versus full operation. The virtue of Idle mode is that ...
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... Stop mode. The same 65536 external clock cycle delay is performed if an external crystal oscillator is used instead of an external crystal. PIN STATES IN POWER SAVING MODES Table 7-1 DEVICE MODE DS80C310 Idle or Stop DS80C320 All Others Idle or Internal program Stop execution Idle All Others ...
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SPEED REDUCTION The High-Speed Microcontroller is a fully CMOS 8051 compatible microcontroller. significantly less power than other 8051 versions because it is more efficient average, software will run 2.5 times faster on the High-Speed Microcontroller than on other ...
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In addition, the DS87C520 and DS87C530 has the capability to operate from the internal ring oscillator during normal operation, not only during the crystal warm-up period. Table 7-3 summarizes the new control bits associated with the power management features. POWER ...
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INTERNAL TIMING RELATIONSHIPS IN PMM1 Figure 7-2 SINGLE-CYCLE INSTRUCTION MACHINE CYCLES C1 ALE INTERNAL CLOCK (PMM1) EXTERNAL CLOCK PMM1 and PMM2 are entered and exited by setting the is possible use the switchback feature to effect a return to the ...
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EFFECT OF CLOCK MODES ON TIMER OPERATION Table 7-4 OSC. OSC. CYCLES CYCLES PER CD1 CD0 MACHINE CYCLE TxM Reserved (PMM1 1024 (PMM2) SWITCHBACK The switchback feature solves one of ...
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The timing of the switchback is dependent on the source. Interrupt–initiated switchbacks will occur at the start of the first C1 cycle following the event initiating the switchback. In PMM, each internal Cx cycle is 16 external clock cycles for ...
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... Stop mode, 0=Crystal or external clock will be the clock source when resuming from Stop mode Note: Upon completion of crystal warm up period, DS80C320 devices will switch to crystal. DS87C520 and DS87C530 devices will switch to clock source designated by XT/RG bit XTOFF PMR.3 Crystal Oscillator Disable ...
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SWITCHING BETWEEN CLOCK SOURCES DS87C520 and DS87C530 incorporate the ability to run the device from the ring oscillator after the crystal warm-up period has elapsed. Immediately following a reset (including initial power-up), all devices must operate from an external crystal ...
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SECTION 8: RESET CONDITIONS The High-Speed Microcontroller provides several ways to place the CPU in a reset state. It also offers the means for software to determine the cause of a reset. The reset state of most processor bits is ...
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The Watchdog Timer is fully described in Section 11. Software can determine that a Watchdog time-out was the reason for the reset by using the Watchdog Timer Reset flag (WTRF). WTRF is located at WDCON.2. Hardware will set this bit ...
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NO-BATTERY RESET The battery backup feature of the DS87C530 introduces a new type of reset condition. Most SFR bits are automatically reset to their default state upon a power-on reset. The external backup battery feature makes some bits non-volatile, however, ...
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SECTION 9: INTERRUPTS The High-Speed Microcontroller family utilizes a three-priority interrupt system. interrupts varies according to the specific device. Each source has an independent priority bit, flag, interrupt vector, and enable. In addition, interrupts can be globally enabled (or disabled). ...
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Each interrupt source has an associated vector. This is the address to which the CPU will jump when the interrupt occurs. When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is ...
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If the Power Management Modes are utilized, the designer must remember that edge triggered interrupts must be high and low for one machine cycle before being recognized. This means that in PMM1 it will require 128 external clock cycles to ...
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Power-fail Interrupt Some devices have the ability to generate an interrupt when V These devices compare V CC interrupt will result (if enabled). Note that the Power-fail Interrupt has the highest priority. The priority level cannot be altered by the ...
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INTERRUPT ACKNOWLEDGE CYCLE The process of acknowledging an interrupt requires multiple machine cycles that begin with the setting of the associated flag. For edge triggered external interrupts and internal interrupt sources, the interrupt flags are set automatically by hardware. For ...
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INTERRUPT FUNCTIONAL DESCRIPTION Figure 9-1 PFI INT0 TF0 IT1 INT1 TF1 RI_0 TI_0 TF2 RI_1 TI_1 INT2 INT3 INT4 INT5 WATCHDOG REAL-TIME CLOCK INTERRUPT FLAG ENABLE BITS BITS HIGHEST PRIORITY LOWEST PRIORITY INDIVIDUAL GLOBAL ENABLES ENABLE 112 of 175 High-Speed ...
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INTERRUPT REGISTER CONFLICTS During normal operation there is a small but finite probability that application software may try to read or modify a register associated with interrupt functions at the same time that the interrupt hardware is modifying the register. ...
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SECTION 10: PARALLEL I/O The High-Speed Microcontroller method of implementing I/O ports follows the standard 8051 convention. This provides backward compatibility with existing designs. All drive capabilities exceed or equal the original 80C32 and voltage levels are compatible. The transitions ...
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PORT 0 General Purpose I/O Devices which have internal program memory have the ability to use Port general purpose I/O. Data written to the port latch serves to set both level and direction of the data on ...
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PORT 0 FUNCTIONAL CIRCUITRY Figure 10-1 INTERNAL DATA BUS D Q WRITE ENABLE READ ENABLE PORT 2 General Purpose I/O Devices which have internal program memory have the ability to use Port 2 for a general purpose I/O. Data written ...
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PORT 2 FUNCTIONAL CIRCUITRY Figure 10-2 ADDRESS A8-A15 INTERNAL DATA BUS WRITE ENABLE READ ENABLE PORTS 1 AND 3 Ports 1 and 3 are general purpose I/O ports with optional special functions associated with each pin. Enabling ...
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OUTPUT FUNCTIONS Although 8051 I/O ports appear to be true I/O, their output characteristics are dependent on the individual port and pin conditions. When software writes a logic 0 to the port for output, the port is pulled to ground. ...
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READ-MODIFY-WRITE INSTRUCTIONS The normal read instructions will read the pin state without regard to the output data latch. The only exception is the read-modify–write category of instructions. They are listed as follows. INSTRUCTION DESCRIPTION ANL Logical AND ORL Logical OR ...
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I/O PORT TIMING FOR MOV INSTRUCTION Figure 10-1 Last Cycle of Previous Instr. & MOV prefetch CLK ALE PSEN P1.0 AD0-AD7 A0-A7 D0-D7 MOV Opcode MOV Address Instruction Opcode PORT 2 A8-A15 OPTIONAL FUNCTIONS Every port pin ...
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SECTION 11: PROGRAMMABLE TIMERS All members of the High-Speed Microcontroller family incorporate three 16-bit programmable timers and some also have a Watchdog Timer with a programmable interval. Because the Watchdog Timer is significantly different from the other timers ...
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TMOD REGISTER SUMMARY TIMER MODE CONTROL TMOD.7 TMOD.6 TMOD.5 TMOD.4 TMOD.3 TMOD.2 TMOD.1 TMOD.0 TCON REGISTER SUMMARY TIMER/COUNTER CONTROL TCON.7 TMOD; 89h GATE - Timer 1 GATE control. When GATE=1, Timer 1 will clock only when and TR1 =1. When ...
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TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 MODE 0 Mode 0 configures either Timer 0 or Timer 1 for operation as a 13-bit Timer/Counter. As shown in Figure 11-1, bits M1=0 and M0=0 of the TMOD register select this operating ...
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TFn flag is set. Timebase selection, counter/timer selection, and the gate function operate as described in mode 0. TIMER/COUNTER 0 AND 1, MODES 0 AND 1 Figure 11-1 OSC INPUT TO TIMER CLK MODE TIMER INPUT ...
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MODE 2 This mode configures the timer as an 8-bit timer/ counter with automatic reload of the start value. This configuration is shown in Figure 11-2, and is selected when bits M1and M0 of the TCON register are set to ...
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TIMER/COUNTER 0 MODE 3 Figure 11-3 OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC/1 PMM1 OSC/16 PMM2 OSC/256 T0 = P3.4 TR0 = TCON.4 GATE = TMOD.3 INT0 = P3.2 TR1 = TCON.6 In Mode 3, ...
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T2CON.5 T2CON.4 T2CON.3 T2CON.2 T2CON.1 T2CON.0 T2MOD REGISTER SUMMARY TIMER TWO MODE CONTROL T2MOD.7-2 T2MOD.1 T2MOD.0 RCLK - Receive Clock Flag. This bit determines whether Timer used for Serial Port 0 timing of received data in ...
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TIMER 2 CAPTURE REGISTERS SUMMARY LEAST SIGNIFICANT BYTE CAPTURE OF TIMER 2 RCAP2L.7-0 MOST SIGNIFICANT BYTE CAPTURE OF TIMER 2 RCAP2H.7-0 TIMER 2 MODES As is seen in the register descriptions, Timer 2 has several abilities not found in Timers ...
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TIMER/COUNTER 2 WITH OPTIONAL CAPTURE Figure 11-4 OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC/1 PMM1 OSC/16 PMM2 OSC/256 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1 EXEN2 = T2CON.3 16-bit Auto-reload Timer/Counter This mode ...
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TIMER/COUNTER 2 AUTO RELOAD MODE Figure 11-5 OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC/1 PMM1 OSC/16 PMM2 OSC/256 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1 EXEN2 = T2CON.3 OSC INPUT TO TIMER CLK ...
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Up/Down Count Auto–reload Timer/Counter The up/down auto-reload counter option is selected by the DCEN (T2MOD.0) bit, and is illustrated in Figure 11-5b. When DCEN is set to a logic 1, Timer 2 will count up or down as controlled by ...
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TIMER/COUNTER 2 BAUD RATE GENERATOR MODE Figure 11-6 OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC/2 PMM1 OSC/82 PMM2 OSC/512 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1 EXEN2 = T2CON.3 Timer Output Clock Generator ...
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TIMER/COUNTER 2 CLOCK OUT MODE Figure 11-7 OSC INPUT TO TIMER CLK MODE TIMER INPUT DIVIDE BY 4 OSC/2 PMM1 OSC/32 PMM2 OSC/512 C/T2 = T2CON.1 F_OUT= OSC INPUT T2 = P1.0 TO TIMER (4*(65536- RCAP2H, RCAP2L)) T2OE = T2MOD.1 ...
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WATCHDOG TIMER The Watchdog Timer is a user programmable clock counter that can serve as a time-base generator, an event timer system supervisor. As can be seen in the diagram of Figure 11-8, the timer is driven by ...
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The Watchdog Timer is a free running timer. When used as a simple timer with both the reset and interrupt functions disabled (EWT = 0 and EWDI = 0), the timer will continue to set the Watchdog Interrupt flag each ...
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The Watchdog time-out selection is made using bits WD1 (CKCON.7) and WD0 (CKCON.6) as shown in the figure. The time-out selections possible are shown in the bit descriptions that follow. The watchdog timeout period is affected by the use of ...
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WDCON.0 Read/write access: CLOCK CONTROL CKCON.7 CKCON.6 The default Watchdog time-out is the shortest one (WD1=WD0=0). Software can change this value easily, so this should cause no inconvenience. However, the EWT, WDIF, and RWT bits are protected under the Timed ...
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SECTION 12: SERIAL I/O The High-Speed Microcontroller serial communication is compatible with the 80C32. This includes framing error detection and automatic address recognition. The High-Speed Microcontroller provides two fully independent UARTs (serial ports) for simultaneous communication over two channels. The ...
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MODE 2 This mode is an asynchronous mode that transmits a total of 11 bits. These include 1 start bit, 8 data bits, a programmable ninth bit, and 1 stop bit. The ninth bit is determined by the value in ...
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SERIAL PORT SCON0; 98h CONTROL ZERO This is the standard 80C32 Serial Port. The new Serial Port is designated Serial Port 1 and is documented below. SCON0.7 SCON0.6 SCON0.4 SCON0.3 SCON0.2 SCON0.0 SM0/FE_0 - Serial Port 0 Mode bit 0 ...
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Initialization: Read/Write Access: SERIAL PORT CONTROL ONE Serial Port 1 performs identically to the standard Serial Port 80C32 with one exception. The baud rate generation from Timer 2 is not available in Modes 1 and 3. Timer ...
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SCON1.1 SCON1.0 Initialization: Read/Write Access: POWER CONTROL PCON.7 PCON.6 WATCHDOG CONTROL WDCON.7 TIMER TWO CONTROL T2CON.5 TI_1 - Flag that indicates the transmitted word has been completely shifted out. In mode set at the end of the ...
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T2CON.4 BAUD RATES Each mode has a baud rate generator associated with it. This generator is generally the same for each UART. Several of the baud rate generation techniques have options and these options are independent for the two UARTs. ...
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Mode These asynchronous modes are commonly used for communication with PCs, modems, and other similar interfaces. The baud rates are programmable using the oscillator input and 16-bit Timer 2 or 8-bit Timer 1. The respective timer is ...
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Setting either RCLK or TCLK to a logic 1 selects Timer 2 for baud rate generation. RCLK and TCLK reside in T2CON.4 and TCON.5 respectively. When using Timer 2 to generate baud rates, the formula will be as ...
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SERIAL PORT MODE 0 Figure 12-1 OSC DIVIDE DIVIDE SM2= SM2= SCONx.5 LDSBUF SCONx.5 RDSBUF LOAD SERIAL BUFFER BAUD CLOCK T1 R1 FLAG = FLAG = SCONx.1 SCONx.0 SERIAL INTERRUPT TRANSMIT TIMING LDSBUF SHIFT ...
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The RXD signal is used for both transmission and reception. TXD provides the shift clock. Data bits enter and exit LSb first. The baud rate is equal to the shift clock frequency. This can be either oscillator divided by 4 ...
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Mode 2 This mode uses a total of 11 bits in asynchronous full duplex communication as illustrated in Figure 12-3. The 11 bits consist of one start bit (a logic 0), 8 data bits, a programmable 9th bit, and one ...
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SERIAL PORT MODE 1 Figure 12-2 TIMER 2 OVERFLOW TIMER 1 OVERFLOW DIVIDE BY 2 SMOD_0 PCON.7 OR SMOD_1= WDCON TCLK = T2CON.4 DIVIDE BY 16 RCLK = T2CON FLAG = SCONx.1 TRANSMIT ...
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SERIAL PORT MODE 2 Figure 12-3 OSC/2= CRYSTAL/2 DIVIDE BY 2 SMOD_0 PCON.7 OR SMOD_1= WDCON.7 DIVIDE FLAG = SCONx.1 TRANSMIT TIMING LDSBUF SHIFT TXD TI RECEIVE TIMING RXD START BIT DETECTOR SAMPLING SHIFT RI ...
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Reception begins when a falling edge is detected as part of the incoming start bit on the RXD pin. The RXD pin is then sampled according to the baud rate speed. The 9 SCON (SCON0.2 or SCON1.2). When a stop ...
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SERIAL PORT MODE 3 Figure 12-4 TIMER 2 OVERFLOW TIMER 1 OVERFLOW DIVIDE BY 2 SMOD_0 PCON.7 OR SMOD_1= WDCON TCLK = T2CON.4 DIVIDE BY 16 RCLK = T2CON FLAG = SCONx.1 TRANSMIT ...
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MULTIPROCESSOR COMMUNICATION Multiprocessor communication mode makes special use of the 9 th original 8051, the 9 bit was restricted condition, but had no special purpose. In the 80C32 and the High-Speed Microcontroller, it can be ...
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Note that an address of 11110000 will reach only microcontroller 1. An address of 11110001 will reach both microcontroller 1 and microcontroller 2. An address of 11110010 will reach only microcontroller 3. The microcontroller will also match on any address ...
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SECTION 13: TIMED ACCESS PROTECTION The High-Speed Microcontroller uses a protection feature called Timed Access to prevent accidental writes to critical SFR bits. These bits could cause a system failure or prevent the Watchdog Timer from doing its job if ...
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This is regardless of whether any bits were modified. Figure 13-1 illustrates a number of examples of correct and incorrect use of the Timed Access procedure. TIMED ACCESS EXAMPLES Figure 13-1 three machine cycles three machine cycles MOV 0C7h, #0AAh ...
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EXAMPLE: A TRANSIENT CAUSES THE WATCHDOG TO BE DISABLED TABLE_READ: C2D2 MOV C2D5 79 FF MOV C2D7 78 90 MOV LOOP: C2D9 E0 MOVX C2DA F6 MOV C2DB 06 INC C2DC A3 INC C2DD ...
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SECTION 14: REAL-TIME CLOCK The DS87C530 incorporates a real-time clock (RTC) onto the High-Speed Microcontroller family core. This allows the device to perform real-time related functions such as data logging and time-stamping without an external timer. In addition, the RTC ...
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Although it may be desired to program the RTC time registers and then start the oscillator, this sequence is not recommended because of the delay incurred by the RTC crystal warm-up period. There are two situations where the RTC will ...
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Writing an invalid time to these registers (loading the RTCM register with 3Dh or 61 minutes, for example) will result in an inaccurate count by the RTC the responsibility of the software to ensure that only valid times ...
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Setting the alarm to cause an interrupt once during a 24-hour period is done by setting all the alarm registers to the desired value and enabling all compare bits. A recurring alarm is enabled by clearing the compare enable bits ...
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CALIBRATING THE RTC OSCILLATOR Although the DS87C530 RTC accuracy is guaranteed for ± 2 minutes per month, users may occasionally require greater accuracy. The RTC incorporates the ability to adjust the internal capacitance of the crystal amplifier via the RTC ...
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SECTION 15: BATTERY BACKUP The DS87C530 incorporates a feature which can maintain timekeeping and on-chip SRAM contents in the absence external energy source such as a lithium battery or 0.47 F super cap can be CC ...
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The registers shown in Table 15-2 are battery-backed, and one or more bits will be indeterminate following a no-battery reset. They should be initialized as part of a no-battery reset procedure. BATTERY BACKED SFRS Table 15-2 REGISTER NAME TRIM RTASS ...
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SECTION 16: INSTRUCTION SET DETAILS Details of flags modified by each instruction are located in Section 4 INSTRUCTION CODE MNEMONIC ADD ADD A, direct ...
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INSTRUCTION CODE MNEMONIC ANL ANL A, direct ANL A, ...
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INSTRUCTION CODE MNEMONIC RLC RRC SWAP ...
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INSTRUCTION CODE MNEMONIC MOV direct #data MOV @Ri ...
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INSTRUCTION CODE MNEMONIC CLR CLR bit SETB SETB bit 1 ...
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INSTRUCTION CODE MNEMONIC ACALL addr LCALL addr ...
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INSTRUCTION CODE MNEMONIC rel JNC rel ...
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MNEMONIC INSTRUCTION CODE DJNZ Rn, rel DJNZ direct,rel ...
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SECTION 17: TROUBLESHOOTING DEVICE OPERATES AT 1/3 OF CRYSTAL SPEED The High-Speed Microcontroller Family operates from the primary or fundamental mode of the external crystal. Many off-the-shelf high-frequency crystals are specified to operate from their third overtone. When used with ...
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... In addition, software timing loops will run faster, possibly changing program operation. These and other effects are described in Application Note 56 (The DS80C320 as a Drop-In Replacement for the 8032). Application Note 57 (DS80C320 Memory Interface Timing) discusses memory interface timing for the DS80C320 ...
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SECTION 18: MICROCONTROLLER DEVELOPMENT SUPPORT TECHNICAL SUPPORT Dallas Semiconductor has a wide range of services designed to support its customers. Microcontroller applications engineers are available Monday through Friday (excluding holidays) to provide technical support from ...