PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 70

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
10.5
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
TABLE 10-1:
DS41211B-page 68
0Bh/8Bh
0Ch
8Ch
9Ah
9Bh
9Ch
9Dh
Legend:
Note 1:
Address
Protection Against Spurious Write
INTCON
PIR1
PIE1
EEDAT
EEADR
EECON1
EECON2
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
EECON2 is not a physical register.
Timer
Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
(1)
(64 ms
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EEPROM Control Register 2
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEIF
EEIE
Bit 7
GIE
—
duration)
ADIE
Bit 6
PEIE
ADIF
—
CCP1IE
CCP1IF
Bit 5
T0IE
—
prevents
Preliminary
INTE
Bit 4
—
—
—
WRERR WREN
CMIE
GPIE
CMIF
Bit 3
10.6
Data memory can be code-protected by programming
the CPD bit in the Configuration Word (Register 12-1)
to ‘0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which
Programming unused locations in program memory to
‘0’ will also help prevent data memory code protection
from becoming breached.
OSFIF
OSFIE
Bit 2
T0IF
outputs
Data EEPROM Operation During
Code-Protect
TMR2IF TMR1IF 000- 0000 000- 0000
TMR2IE TMR1IE 000- 0000 000- 0000
Bit 1
INTF
WR
the
GPIF
contents
Bit 0
 2004 Microchip Technology Inc.
RD
0000 0000 0000 0000
---- x000 ---- q000
---- ---- ---- ----
POR, BOD
Value on
of
data
Value on
all other
Resets
memory.