PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 173

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.2.1
The QEI module shares its input pins with the Input
Capture module. The inputs are mutually exclusive;
only the IC module or the QEI module (but not both)
can be enabled at one time. Also, because the IC and
QEI are multiplexed to the same input pins, the
programmable noise filters can be dedicated to one
module only.
REGISTER 16-2:
 2003 Microchip Technology Inc.
QEI CONFIGURATION
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
Note 1: QEI must be enabled and in Index mode.
2: QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and
3: Enabling one of the QEI operating modes remaps the IC buffer registers CAP1BUFH,
4: ERROR bit must be cleared in software.
QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER
bit 7
VELM: Velocity Mode bit
1 = Velocity mode disabled
0 = Velocity mode enabled
ERROR: QEI error bit
1 = Position counter
0 = No overflow or underflow
UP/DOWN: Direction of Rotation Status bit
1 = Forward
0 = Reverse
QEIM2:QEIM0: QEI Mode bits
111 =Unused
110 =QEI enabled in 4x Update mode; position counter reset on period match
101 =QEI enabled in 4x Update mode; INDX resets the position counter
100 =Unused
010 =QEI enabled in 2x Update mode; position counter reset on period match
001 =QEI enabled in 2x Update mode; INDX resets the position counter
000 =QEI off
PDEC1:PDEC0: Velocity Pulse Reduction Ratio bit
11 =1:64
10 =1:16
01 =1:4
00 =1:1
Legend:
R = Readable bit
-n = Value at POR
R/W-0
VELM
IC modules are both enabled, QEI will take precedence.
CAP1BUFL, CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL as the VREGH,
VREGL, POSCNTH, POSCNTL, MAXCNTH, and MAXCNTL registers (respectively) for the
QEI.
(POSCNT = MAXCNT)
(POSCNT = MAXCNT)
ERROR
R/W-0
(4)
(1)
PIC18F2331/2431/4331/4431
overflow or underflow
UP/DOWN
R-0
Preliminary
W = Writable bit
‘1’ = bit is set
(2,3)
QEIM2
R/W-0
The operation of the QEI is controlled by the QEICON
configuration register. See Register 16-2.
(1)
Note:
QEIM1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
In the event that both QEI and IC are
enabled, QEI will take precedence and IC
will remain disabled.
QEIM0
R/W-0
x = bit is unknown
PDEC1
R/W-0
DS39616B-page 171
PDEC0
R/W-0
bit 0