PIC24FJ256GB210-I/PT Microchip Technology Inc., PIC24FJ256GB210-I/PT Datasheet - Page 117
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC24FJ256GB210-I/PT
Manufacturer Part Number
PIC24FJ256GB210-I/PT
Description
100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ256GB206-IPT.pdf
(386 pages)
Specifications of PIC24FJ256GB210-I/PT
A/d Inputs
24 Channel, 10-bit
Comparators
3
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
84
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Ram Size
98K Bytes
Speed
32 MHz
Temperature Range
–40 to 85 °C
Timers
5-16-bit
Voltage, Range
2.2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GB210-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 117 of 386
- Download datasheet (4Mb)
REGISTER 7-21:
2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6-4
bit 3
bit 2-0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
CNIP<2:0>: Input Change Notification Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
CMIP<2:0>: Comparator Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
MI2C1IP2
CNIP2
R/W-1
R/W-1
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
W = Writable bit
‘1’ = Bit is set
MI2C1IP1
CNIP1
R/W-0
R/W-0
MI2C1IP0
PIC24FJ256GB210 FAMILY
CNIP0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
SI2C1IP2
CMIP2
R/W-1
R/W-1
x = Bit is unknown
SI2C1IP1
CMIP1
R/W-0
R/W-0
DS39975A-page 117
SI2C1IP0
CMIP0
R/W-0
R/W-0
bit 8
bit 0
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