PIC24FJ256GB210-I/PT Microchip Technology Inc., PIC24FJ256GB210-I/PT Datasheet - Page 40

• Manufacturer Part Number: PIC24FJ256GB210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB210-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC24FJ256GB210 FAMILY
3.2
REGISTER 3-1:
DS39975A-page 40
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0, HSC
IPL2
U-0
—
2:
CPU Control Registers
(2)
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
The IPL Status bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
(1)
R/W-0, HSC
Unimplemented: Read as ‘0’
DC: ALU Half Carry/Borrow bit
1 = A carry out from the 4
0 = No carry out from the 4
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15); user interrupts are disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
N: ALU Negative bit
1 = Result was negative
0 = Result was not negative (zero or positive)
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
Z: ALU Zero bit
1 = An operation, which affects the Z bit, has set it at some time in the past
0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
C: ALU Carry/Borrow bit
1 = A carry out from the Most Significant bit of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
IPL1
of the result occurred
SR: ALU STATUS REGISTER
U-0
—
(2)
(1)
W = Writable bit
R/W-0, HSC
HSC = Hardware Settable/Clearable bit
‘1’ = Bit is set
IPL0
U-0
—
(2)
th
low-order bit (for byte-sized data) or 8
th
(1)
or 8
R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
th
U-0
RA
low-order bit of the result has occurred
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
N
(1,2)
U-0
OV
—
th
low-order bit (for word-sized data)
 2010 Microchip Technology Inc.
x = Bit is unknown
U-0
—
Z
R/W-0, HSC
DC
C
bit 8
bit 0