PIC24FJ256GB210-I/PT Microchip Technology Inc., PIC24FJ256GB210-I/PT Datasheet - Page 320
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PIC24FJ256GB210-I/PT
Manufacturer Part Number
PIC24FJ256GB210-I/PT
Description
100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ256GB206-IPT.pdf
(386 pages)
Specifications of PIC24FJ256GB210-I/PT
A/d Inputs
24 Channel, 10-bit
Comparators
3
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
84
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Ram Size
98K Bytes
Speed
32 MHz
Temperature Range
–40 to 85 °C
Timers
5-16-bit
Voltage, Range
2.2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
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modules are related in this application. This example
PIC24FJ256GB210 FAMILY
25.2
Time measurements on the pulse width can be similarly
performed using the A/D module’s internal capacitor
(C
Figure 25-2 shows the external connections used for
time measurements, and how the CTMU and A/D
also shows both edge events coming from the external
CTEDG pins, but other configurations using internal
edge sources are possible. A detailed discussion on
measuring capacitance and time with the CTMU module
is provided in the “PIC24F Family Reference Manual”.
25.3
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
FIGURE 25-2:
FIGURE 25-3:
DS39975A-page 320
AD
) and a precision resistor for current calibration.
Measuring Time
Pulse Generation and Delay
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
TIME MEASUREMENT
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
CTEDG1
C2INB
C
DELAY
CTEDG1
CTEDG2
ANx
R
PR
EDG1
CV
Current Source
PIC24F Device
Comparator
REF
CTMU
C2
EDG2
EDG1
C
AD
PIC24F Device
When the module is configured for pulse generation
delay by setting the TGEN (CTMUCON<12>) bit, the
internal current source is connected to the B input of
Comparator 2. A capacitor (C
the Comparator 2 pin, C2INB, and the comparator volt-
age reference, CV
is then configured for a specific trip point. The module
begins to charge C
detected. When C
point, a pulse is output on CTPLS. The length of the
pulse delay is determined by the value of C
the CV
Figure 25-3 shows the external connections for pulse
generation, as well as the relationship of the different
analog modules required. While CTEDG1 is shown as
the input pulse source, other options are available. A
detailed discussion on pulse generation with the CTMU
module is provided in the “PIC24F Family Reference
Manual”.
A/D Converter
Current Source
CTMU
REF
Output Pulse
trip point.
DELAY
REF
DELAY
CTPLS
, is connected to C2INA. CV
2010 Microchip Technology Inc.
charges above the CV
when an edge event is
DELAY
) is connected to
DELAY
REF
and
REF
trip
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