DSPIC30F2012-20I/SP Microchip Technology Inc., DSPIC30F2012-20I/SP Datasheet - Page 93
DSPIC30F2012-20I/SP
Manufacturer Part Number
DSPIC30F2012-20I/SP
Description
16 BIT MCU/DSP 28LD 20MIPS 12 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F2012-20ISP.pdf
(204 pages)
Specifications of DSPIC30F2012-20I/SP
A/d Inputs
10-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
20
Interface
I2C/SPI/UART, USART
Ios
20
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SPDIP
Programmable Memory
12K Bytes
Ram Size
1K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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13.3
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDOx pin is driven. When SS1 pin goes high, the
SDOx pin is no longer driven. Also, the SPI module is
resynchronized, and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb
even if SS1 had been de-asserted in the middle of a
transmit/receive.
13.4
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
© 2006 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
dsPIC30F2011/2012/3012/3013
13.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
SPI Operation During CPU Idle
Mode
DS70139D-page 91
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